High voltage metal-oxide-semiconductor transistor device
A high voltage metal-oxide-semiconductor transistor device includes a substrate, at least an isolation structure formed in the substrate, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective sides of the gate. The isolation structure further includes a recess. The gate includes a first gate portion formed on a surface of the substrate and a second gate portion downwardly extending from the first gate portion and formed in the recess.
1. A high voltage metal-oxide-semiconductor (HV MOS) transistor device comprising:
a substrate;
at least an isolation structure formed in the substrate, the isolation structure having a recess formed therein;
a gate formed on the substrate, the gate further comprising:
a first gate portion formed on a surface of the substrate; and
a second gate portion downwardly extending from the first gate portion and formed in the recess;
a gate dielectric layer formed under and contacting both the first gate portion and the second gate portion; and
a source region and a drain region formed in the substrate at respective sides of the gate.
2. The HV MOS transistor device according to claim 1 , wherein the first gate portion and the second gate portion are perpendicular to each other.
3. The HV MOS transistor device according to claim 1 , wherein the first gate portion and the second gate portion physically contact to each other.
4. The HV MOS transistor device according to claim 1 , wherein the second gate portion comprises a continuous shape.
5. The HV MOS transistor device according to claim 4 , wherein the second gate portion comprises a U-shaped second gate portion having an opening toward the source region.
6. The HV MOS transistor device according to claim 4 , wherein the second gate portion comprises a comb-shaped second gate portion.
7. The HV MOS transistor device according to claim 1 , wherein the second gate portion comprises a non-continuous islanding second gate portion.
8. The HV MOS transistor device according to claim 7 , wherein the isolation structure interrupts into the non-continuous islanding second gate portion.
9. The HV MOS transistor device according to claim 1 , wherein the first gate portion covers the second gate portion entirely.
10. The HV MOS transistor device according to claim 9 , wherein the first gate portion and the second gate portion form a T-shaped gate.
11. The HV MOS transistor device according to claim 9 , wherein the first gate portion and the second gate portion form an L-shaped gate.
12. The HV MOS transistor device according to claim 9 , wherein the first gate portion covers a portion of the second gate portion.
13. The HV MOS transistor device according to claim 1 , wherein the isolation structure electrically isolates the second gate portion and the substrate.
14. The HV MOS transistor device according to claim 1 , wherein the gate dielectric layer is formed in between the first gate portion and the substrate.
15. The HV MOS transistor device according to claim 14 , wherein the gate dielectric layer is further formed in between the second gate portion and the substrate.
16. The HV MOS transistor device according to claim 1 , wherein a depth of the recess is smaller than a depth of the isolation structure.
17. The HV MOS transistor device according to claim 16 , wherein a thickness of the second gate portion is smaller than the depth of the recess.
18. The HV MOS transistor device according to claim 1 , wherein a width of the second gate portion is smaller than a width of the isolation structure.
19. The HV MOS transistor device according to claim 1 , further comprising a doped region formed in the substrate, and the gate covers a portion of the doped region.
20. The HV MOS transistor device according to claim 19 , wherein the doped region further comprises a plurality of finger portions extending toward the drain region.