Copper pillar full metal via electrical circuit structure
An electrical interconnect including a first circuitry layer with a first surface and a second surface. At least a first dielectric layer is printed on the first surface of the first circuitry layer to include a plurality of first recesses. A conductive material is deposited in a plurality of the first recesses to form a plurality of first conductive pillars electrically coupled to, and extending generally perpendicular to, the first circuitry layer. At least a second dielectric layer is printed on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive pillars. A conductive material is deposited in a plurality of the second recesses to form a plurality of second conductive pillars electrically coupled to, and extending parallel the first conductive pillars.
1. A method of making an electrical interconnect comprising the steps of:
providing a first circuitry layer comprising a first surface and a second surface;
applying at least a first dielectric layer on the first surface of the first circuitry layer to include a plurality of first recesses;
plating a conductive material that substantially fills a plurality of the first recesses comprising a plurality of first conductive pillars electrically coupled to, and extending generally perpendicular to, the first circuitry layer;
planarizing the first conductive pillars and the first dielectric layer before applying the second dielectric layer;
applying at least a second dielectric layer on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive pillars;
plating a conductive material that substantially fills a plurality of the second recesses comprising a plurality of second conductive pillars electrically coupled to, and extending parallel to the first conductive pillars; and
electrically coupling contact pads on an IC device to a plurality of the second conductive pillars.
2. The method of claim 1 comprising the step of printing at least one electrical device on one of the dielectric layers and electrically coupling the printed electrical device to at least a portion of the first circuitry layer.
3. The method of claim 1 comprising the steps of:
locating a second circuitry layer on the second dielectric layer and electrically coupling the second circuitry layer with a plurality of the second conductive pillars; and
applying at least a third dielectric layer on the second dielectric layer to include a plurality of third recesses generally aligned with a plurality of the second conductive pillars.
4. The method of claim 3 comprising etching away portions of the second circuitry layer located in the third recesses away to expose a plurality of the second conductive pillars.
5. The method of claim 3 comprising the steps of:
plating a conductive material in a plurality of the third recesses comprising a plurality of third conductive pillars electrically coupled to, and extending parallel the second conductive pillars; and
electrically coupling contact pads on an IC device to a plurality of the third conductive pillars, wherein the step of electrically coupled comprises one of a flip chip attachment directly to a plurality of third pillars, solder balls, or wire bonding.
6. The method of claim 3 comprising the steps of:
locating a third circuitry layer on the third dielectric layer; and
attaching a covering layer to the third circuitry layer, the covering layer comprising a plurality of openings exposing contact pads on the third circuitry layer configured to electrically couple with an IC device.
7. The method of claim 1 comprising attaching a covering layer to the second surface of the first circuitry layer, the covering layer comprising a plurality of openings exposing a plurality of contact pads on the first circuitry layer adapted to electrically couple with a PCB.
8. The method of claim 1 comprising locating a dielectric material in one or more of the recesses to surround one or more conductive pillars.
9. A method of making an electrical interconnect comprising the steps of:
providing a first circuitry layer comprising a first surface and a second surface;
applying a first liquid dielectric layer on the first surface of the first circuitry layer;
imaging the first liquid dielectric layer to form a first dielectric layer with a plurality of first recesses;
plating a conductive material that substantially fills a plurality of the first recesses comprising a plurality of first conductive pillars electrically coupled to, and extending generally perpendicular to, the first circuitry layer;
planarizing the first conductive pillars and the first dielectric layer;
applying a second liquid dielectric layer on the first dielectric layer;
imaging the second liquid dielectric layer to form second dielectric layer with a plurality of second recesses generally aligned with a plurality of the first conductive pillars; and
plating a conductive material that substantially fills a plurality of the second recesses comprising a plurality of second conductive pillars electrically coupled to, and extending from the first conductive pillars; and
printing at least one electrical device on one of the dielectric layers and electrically coupling the electrical device to at least a portion of the circuitry layers.
10. The method of claim 1 comprising the step of plating sidewalls of the first recesses to facilitate plating of the first conductive pillars.
11. The method of claim 1 comprising the step of planarizing the second conductive pillars and the second dielectric layer.
12. A method of making an electrical interconnect comprising the steps of:
providing a first circuitry layer comprising a first surface and a second surface;
applying a first liquid dielectric layer on the first surface of the first circuitry layer;
imaging the first liquid dielectric layer to form a plurality of first recesses;
plating sidewalls of the first recesses;
plating a conductive material that substantially fills a plurality of the first recesses comprising a plurality of first conductive pillars electrically coupled to, and extending generally perpendicular to, the first circuitry layer;
planarizing the first conductive pillars and the first dielectric layer;
applying a second liquid dielectric layer on the first dielectric layer;
imaging the second liquid dielectric layer to form a plurality of second recesses generally aligned with a plurality of the first conductive pillars; and
plating a conductive material that substantially fills a plurality of the second recesses comprising a plurality of second conductive pillars electrically coupled to, and extending from the first conductive pillars.