Semiconductor integrated circuit and power-supply voltage adaptive control system
A semiconductor integrated circuit has: N input terminals; N output terminals; a plurality of flip-flops including N flip-flops and R redundant flip-flops; a selector section configured to select N selected flip-flops from the plurality of flip-flops depending on reconfiguration information and to switch data flow such that data input to the N input terminals are respectively output to the N output terminals by the N selected flip-flops; and an error detection section. At a test mode, the N flip-flops form a scan chain and a scan data is input to the scan chain. The error detection section detects an error flip-flop included in the N flip-flops based on scan input/output data respectively input/output to/from the N flip-flops at the test mode and further generates the reconfiguration information such that the detected error flip-flop is excluded from the N selected flip-flops.
1. A semiconductor integrated circuit comprising:
N input terminals, wherein N is an integer equal to or more than 1;
N output terminals;
a plurality of flip-flops including N flip-flops and R redundant flip-flops, wherein R is an integer equal to or more than 1;
a selector section configured to select N selected flip-flops from said plurality of flip-flops depending on reconfiguration information and to switch data flow such that data input to said N input terminals are respectively output to said N output terminals by said N selected flip-flops; and
an error detection section configured to generate said reconfiguration information at a test mode,
wherein at said test mode, said N flip-flops form a scan chain and a scan data is input to said scan chain,
wherein a flip-flop whose output is fixed to 0 or 1 is an error flip-flop, and
wherein said error detection section detects said error flip-flop included in said N flip-flops based on scan input data respectively input to said N flip-flops and scan output data respectively output from said N flip-flops at said test mode and further generates said reconfiguration information excluding said detected error flip-flop from said N selected flip-flops.
2. The semiconductor integrated circuit according to claim 1 ,
wherein said error detection section comprises a memory section in which said reconfiguration information generated is stored, and
wherein at a predetermined timing after said test mode is ended, said reconfiguration information stored in said memory section is output to said selector section.
3. The semiconductor integrated circuit according to claim 2 ,
wherein said memory section is a latch circuit.
4. The semiconductor integrated circuit according to claim 1 ,
wherein said error detection section comprises N XNOR circuits,
wherein said scan input data respectively input to said N flip-flops and said scan output data respectively output from said N flip-flops are respectively input to input terminals of said N XNOR circuits, and
wherein 0 and 1 are alternately input as said scan data to said scan chain.