Method and apparatus for power amplifier linearization

1. A circuit comprising:

a variable group delay configured to delay a wideband input signal to obtain a delayed input signal;

a wideband operational amplifier configured to determine an error signal based on a difference between the delayed input signal and a linearized power amplifier output;

a feedback amplifier configured to amplify the error signal to obtain an amplified error signal; and

a directional combiner configured to combine the amplified error signal with a power amplifier output to obtain the linearized power amplifier output,

wherein the feedback amplifier comprises:

another variable group delay configured to delay the error signal to obtain a delayed error signal;

another wideband operational amplifier configured to determine another error signal based on a difference between the delayed error signal and the amplified error signal;

another feedback amplifier configured to amplify the another error signal to obtain another amplified error signal; and

another directional combiner configured to combine the another amplified error signal with an output of the feedback amplifier to obtain the amplified error signal.

2. The circuit of claim 1 comprising an integrated circuit fabricated using deep sub-micron CMOS technology.

3. The circuit of claim 1 in combination with a power amplifier.

4. A method of linearizing the output of a power amplifier, the method comprising:

delaying a wideband input signal to obtain a delayed input signal;

determining an error signal based on a difference between the delayed input signal and a linearized power amplifier output;

amplifying the error signal to obtain an amplified error signal; and

combining the amplified error signal with the power amplifier output to obtain the linearized power amplifier output, wherein amplifying the error signal comprises:

delaying the error signal to obtain a delayed error signal;

determining another error signal based on a difference between the delayed error signal and the amplified error signal;

amplifying the another error signal to obtain another amplified error signal; and

combining the another amplified error signal with an output of the feedback amplifier to obtain the amplified error signal.

5. The method of claim 4 further including amplifying the input signal.

6. The circuit of claim 1 , wherein the wideband operational amplifier includes a first input configured to receive the delayed input signal.

7. The circuit of claim 6 , further comprising a directional coupler, wherein the wideband operational amplifier includes a second input configured to receive a coupled signal generated by the directional coupler.

8. The circuit of claim 7 , further comprising a splitter configured to split an input signal to generate the wideband input signal and a power amplifier input signal.

9. The circuit of claim 8 , further comprising a power amplifier configured to receive the power amplifier input signal and to generate the power amplifier output.

10. The circuit of claim 1 , wherein the variable group delay comprises a wideband signal processor.

11. The circuit of claim 10 , wherein the wideband signal processor comprises a plurality of biquad processors arranged in series.

12. The circuit of claim 11 , further comprising a serial peripheral interface configured to control a group delay of the plurality of biquad processors.

13. The circuit of claim 1 , wherein the wideband operational amplifier comprises a plurality of field effect transistors.

14. The method of claim 4 , further comprising receiving the delayed input signal at a first input of a wideband operational amplifier.

15. The method of claim 14 , further comprising generating a coupled signal using a directional coupler, and receiving the coupled signal at a second input of the wideband operational amplifier.

16. The method of claim 15 , further comprising determining the error signal based on amplifying a difference between the delayed input signal and the coupled signal using the wideband operational amplifier.

17. The method of claim 14 , further comprising splitting an input signal to generate the wideband input signal and a power amplifier input signal.

18. The method of claim 17 , further comprising generating the power amplifier output by amplifying the power amplifier input signal.

19. The method of claim 4 , wherein delaying the wideband input signal comprises providing delay using a wideband signal processor.

20. The method of claim 19 , further comprising controlling a group delay of a plurality of biquad processors of the wideband signal processor.