IP Library Granted Patent US 9,012,953
Granted Patent B2
US 9,012,953 · App. 14/175,623 · Granted Apr 21, 2015

LED with improved injection efficiency

Inventors: Steven Lester (Sunnyvale, CA); Jeff Ramer (Sunnyvale, CA); Jun Wu (San Ramon, CA); Ling Zhang (San Jose, CA)
Assignee: Kabushiki Kaisha Toshiba
H01L33/22H01L21/0237H01L21/0243H01L21/02458H01L21/02494H01L21/02505H01L21/0254H01L21/0262H01L21/02658H01L33/20H01L33/06H01L33/025H01L33/32H01L33/007
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Quick Facts
Patent No.
US 9,012,953
App. No.
14/175,623
Granted
Apr 21, 2015
Kind
B2
Abstract

A light emitting device and method for making the same is disclosed. The light-emitting device includes an active layer sandwiched between a p-type semiconductor layer and an n-type semiconductor layer. The active layer emits light when holes from the p-type semiconductor layer combine with electrons from the n-type semiconductor layer therein. The active layer includes a number of sub-layers and has a plurality of pits in which the side surfaces of a plurality of the sub-layers are in contact with the p-type semiconductor material such that holes from the p-type semiconductor material are injected into those sub-layers through the exposed side surfaces without passing through another sub-layer. The pits can be formed by utilizing dislocations in the n-type semiconductor layer and etching the active layer using an etching atmosphere in the same chamber used to deposit the semiconductor layers without removing the partially fabricated device.

Claims (18)

1. A light emitting device comprising:

an n-type semiconductor layer, the n-type semiconductor layer including random dislocations;

an active layer comprising a plurality of sub-layers on the n-type semiconductor layer, the active layer including pits of a density between 10 7 cm −2 and 10 10 cm −2 located on the random dislocations, a plurality of the sub-layers having sidewalls that are bounded by the pits and exposed to the pits, bottoms of the pits located in the n-type semiconductor layer;

a p-type semiconductor layer over the active layer, the p-type semiconductor layer extending into the pits and contacting the exposed sidewalls of the sub-layers and an upper surface of the active layer; and

contact electrodes configured to apply a potential difference between the p-type semiconductor layer and the n-type semiconductor layer.

2. The light emitting device of claim 1 , wherein the n-type semiconductor layer is formed on a substrate, the n-type semiconductor layer having a lattice constant that is different from that of a substrate, the difference giving rise to the random dislocations.

3. The light emitting device of claim 1 , wherein the active layer is formed on a c-plane facet of a material in a GaN family of materials.

4. The light emitting device of claim 1 , wherein holes are injected from the p-type semiconductor layer into the active layer, and the active layer and the p-type semiconductor layer are formed so that at least 10 percent of the holes are injected from the p-type semiconductor layer into the active layer through the exposed sidewalls of the sub-layers.

5. The light emitting device of claim 1 , wherein the n-type semiconductor layer and the p-type semiconductor layer comprise GaN family materials.

6. A light emitting device comprising:

an n-type semiconductor layer, the n-type semiconductor layer including random dislocations;

an active layer comprising a plurality of sub-layers on the n-type semiconductor layer, the active layer including pits of a density between 10 7 cm −2 and 10 10 cm −2 located on the random dislocations, a plurality of the sub-layers having sidewalls that are bounded by the pits, bottoms of the pits located in the n-type semiconductor layer;

a p-type semiconductor layer over the active layer, the p-type semiconductor layer extending into the pits and contacting the sidewalls of the sub-layers and an upper surface of the active layer; and

contact electrodes configured to apply a potential difference between the p-type semiconductor layer and the n-type semiconductor layer.

7. The light emitting device of claim 6 , wherein the n-type semiconductor layer is formed on a substrate, the n-type semiconductor layer having a lattice constant that is different from that of a substrate, the difference giving rise to the random dislocations.

8. The light emitting device of claim 6 , wherein the active layer is formed on a c-plane facet of a material in a GaN family of materials.

9. The light emitting device of claim 6 , wherein holes are injected from the p-type semiconductor layer into the active layer, and the active layer and the p-type semiconductor layer are formed so that at least 10 percent of the holes are injected from the p-type semiconductor layer into the active layer through the sidewalls of the sub-layers.

10. The light emitting device of claim 6 , wherein the n-type semiconductor layer and the p-type semiconductor layer comprise GaN family materials.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2018
From: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 046986/0159 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2018
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 046364/0164 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2014
From: LESTER, STEVEN; RAMER, JEFF; WU, JUN; ZHANG, LING
To: BRIDGELUX, INC.
Reel/Frame 033242/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2014
From: BRIDGELUX, INC.
To: TOSHIBA TECHNO CENTER INC.
Reel/Frame 033242/0456 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2014
From: TOSHIBA TECHNO CENTER INC.
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 033242/0477 →
Continuity (3)
Continuation 13959297 · Aug 5, 2013
Division 12626474 · Nov 25, 2009
Related Publication 20140151728A1 · Jun 5, 2014