Semiconductor structure and process thereof
View Patent ↗A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial structures. The first gate and the second gate are located on a substrate. The first spacer and the second spacer are respectively located on the substrate beside the first gate and the second gate. The first epitaxial structures and the second epitaxial structures are respectively located in the substrate beside the first spacer and the second spacer, wherein the first spacer and the second spacer have different thicknesses, and the spacing between the first epitaxial structures is different from the spacing between the second epitaxial structures. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.
1. A semiconductor structure, comprising:
a first gate and a second gate located on a substrate;
a first spacer and a second spacer respectively located only on the sidewalls of the first gate and the second gate; and
two first epitaxial structures and two second epitaxial structures respectively located in the substrate beside the first spacer and the second spacer, wherein the first spacer and the second spacer have different thicknesses, and the spacing between the two first epitaxial structures is different from the spacing between the two second epitaxial structures.
2. The semiconductor structure according to claim 1 , wherein the first spacer comprises a single spacer and the second spacer comprises a dual spacer.
3. The semiconductor structure according to claim 2 , wherein the dual spacer comprises an internal spacer and an outer spacer.
4. The semiconductor structure according to claim 3 , wherein the material of the outer spacer is common to the material of the first spacer.
5. The semiconductor structure according to claim 3 , wherein the material of the outer spacer is different from the material of the internal spacer.
6. The semiconductor structure according to claim 3 , further comprising:
a buffer layer located between the internal spacer and the outer spacer.
7. The semiconductor structure according to claim 1 , wherein the width of the first gate at the direction of the gate channel length is shorter than the width of the second gate at the direction of the gate channel length.
8. The semiconductor structure according to claim 1 , wherein the first gate and the second gate are of the same conductive type.
9. The semiconductor structure according to claim 1 , wherein the minimum distance between each of the first epitaxial structures and the first gate is shorter than the minimum distance between each of the second epitaxial structures and the second gate.
10. The semiconductor structure according to claim 9 , wherein the minimum distance between each of the first epitaxial structures and the first gate is zero.
11. The semiconductor structure according to claim 1 , wherein the first gate and the second gate all comprise a buffer layer and a dielectric layer having a high dielectric constant located on the substrate from bottom to top, and the second gate further comprises a dielectric layer located between the substrate and the buffer layer.
12. The semiconductor structure according to claim 11 , wherein the buffer layer and the dielectric layer having a high dielectric constant all have U-shaped cross-sectional profiles and the dielectric layer has a “-”-shaped cross-sectional profile.