Method for self-aligned removal of a high-K gate dielectric above an STI region
By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.
1. A method, comprising:
forming a gate layer stack above a semiconductor layer, said gate layer stack comprising a high-k dielectric layer and a metal-containing material formed on said high-k dielectric layer;
forming a trench isolation structure in said gate layer stack, said trench isolation structure extending through said gate layer stack and into said semiconductor layer to isolate a first active region from a second active region;
forming a first gate electrode of a first transistor above said first active region and a second gate electrode of a second transistor above said second active region; and
forming a conductive material above said metal-containing material and directly overlying a top surface of said trench isolation structure, said conductive material forming an electrically conductive connection between said first gate electrode and said second gate electrode.
2. The method of claim 1 , wherein forming said gate layer stack comprises forming said high-k dielectric layer on said semiconductor layer including said first and second active regions and forming a first portion of said metal-containing material above said first active region and a second portion of said metal-containing material above said second active region, said first portion having a first work function differing from a second work function of said second portion.
3. The method of claim 2 , wherein forming said gate layer stack further comprises forming a conductive non-metal layer above said metal-containing material.
4. The method of claim 1 , wherein said conductive material is a polysilicon material.
5. The method of claim 3 , further comprising forming a pad layer above said metal-containing material and using said pad layer as a stop layer during a chemical mechanical polishing process for removing excess material formed during forming said trench isolation structure.
6. The method of claim 5 , wherein said pad layer is formed prior to forming a trench of said trench isolation structure.
7. The method of claim 5 , wherein said pad layer is formed after forming a trench of said trench isolation structure.
8. The method of claim 6 , further comprising forming an etch stop layer prior to forming said pad layer and removing said pad layer after forming said trench isolation structure by an etch process using said etch stop layer as an etch stop.
9. The method of claim 1 , further comprising forming said first and second active regions by using a masking regime based on an alignment mark formed in said semiconductor layer.
10. A method, comprising:
forming a gate layer stack on a semiconductor layer, said gate layer stack comprising a high-k dielectric material and covering a first active region and a second active region;
forming a trench isolation structure that extends through said gate layer stack and into said semiconductor layer so as to isolate said first and second active regions from each other and to provide a first portion of said gate layer stack and a second portion of said gate layer stack;
forming a conductive connection between said first and second portions of said gate layer stack above said trench isolation structure, said conductive connection directly overlying a top surface of the trench isolation structure; and
forming a first transistor in and above said first active region and a second transistor in and above said second active region.
11. The method of claim 10 , wherein forming said gate layer stack comprises forming said high-k material on said semiconductor layer and forming a first metal-containing material having a first work function on said high-k material above said first active region and a second metal-containing material having a second work function on said high-k material above said second active region, said first and second work functions differing from each other.
12. The method of claim 11 , wherein forming said gate layer stack further comprises forming a conductive material above said first and second metal-containing materials.
13. The method of claim 12 , wherein said conductive material is a semiconductor material.
14. The method of claim 10 , further comprising forming a pad layer above said gate layer stack and using said pad layer as a stop layer during a chemical mechanical polishing process used for forming said trench isolation structure.
15. The method of claim 14 , further comprising forming an etch stop layer prior to forming said pad layer, said etch stop layer having a high etch resistance compared to said pad layer.
16. The method of claim 10 , wherein said conductive connection is formed of a semiconductor material.
17. The method of claim 10 , wherein forming said first and second active regions comprises forming an alignment mark in said semiconductor layer and forming implantation masks on the basis of said alignment mark.
18. The method of claim 1 , wherein forming said trench isolation structure comprises forming a trench opening by performing an etch process to etch through said metal-containing material prior to etching through said high-k dielectric layer and prior to etching into said semiconductor layer.
19. The method of claim 10 , wherein forming said gate layer stack comprises forming a metal-containing material above said high-k dielectric material, and wherein forming said trench isolation structure comprises forming said trench isolation structure to extend completely through said high-k dielectric material and said metal-containing material.
20. A method, comprising:
forming a gate layer stack above a semiconductor layer, wherein forming said gate layer stack comprises forming a high-k dielectric material layer above said semiconductor layer, forming a metal-containing material layer above said high-k dielectric material layer, and forming a first conductive material layer above said metal-containing material layer;
forming a trench isolation structure through said gate layer stack to isolate a first active region from a second active region, wherein an upper end of said trench isolation structure extends at least partially into said first conductive material layer above said metal-containing material layer and a lower end of said trench isolation structure extends at least partially into said semiconductor layer below said high-k dielectric material layer;
forming a first gate electrode of a second transistor above said second active region from said gate layer stack;
forming a second gate electrode of a second transistor above said second active region from said gate layer stack; and
forming a second conductive material layer above said first conductive material layer and directly overlying a top surface of said trench isolation structure, said second conductive material layer forming an electrically conductive connection between said first gate electrode and said second gate electrode.