IP Library Granted Patent US 9,024,443
Granted Patent B2
US 9,024,443 · App. 13/836,215 · Granted May 5, 2015

Semiconductor device and manufacturing method thereof

Inventors: Merii Inaba (Yokkaichi, JP); Takeshi Hizawa (Mie-gun, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L23/52H01L21/768H01L23/5226H01L23/5329H01L23/53295H01L21/76804H01L27/11519H01L27/11565H01L2924/0002
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,024,443
App. No.
13/836,215
Granted
May 5, 2015
Kind
B2
Abstract

A semiconductor device according to the present embodiment includes a semiconductor substrate. A lower-layer wiring is provided above a surface of the semiconductor substrate. An interlayer dielectric film is provided on the lower-layer wiring and includes a four-layer stacked structure. A contact plug contains aluminum. The contact plug is filled in a contact hole formed in the interlayer dielectric film in such a manner that the contact plug reaches the lower-layer wiring. Two upper layers and two lower layers in the stacked structure respectively have tapers on an inner surface of the contact hole. The taper of two upper layers and the taper of two lower layers have different angles from each other.

Claims (18)

1. A semiconductor device comprising:

a semiconductor substrate;

a lower-layer wiring provided above a surface of the semiconductor substrate;

an interlayer dielectric film provided on the lower-layer wiring and including a four-layer stacked structure; and

a contact plug containing aluminum, the contact plug being filled in a contact hole formed in the interlayer dielectric film in such a manner that the contact plug reaches the lower-layer wiring, wherein

two upper layers and two lower layers in the stacked structure respectively have tapers on an inner surface of the contact hole, the taper of two upper layers and the taper of two lower layers have different angles from each other.

2. The device of claim 1 , wherein the lower-layer wiring is a wiring containing copper.

3. The device of claim 1 , wherein the two upper layers respectively have a first taper on the inner surface of the contact hole, the first taper inclines at a first angle with respect to the surface of the semiconductor substrate,

the two lower layers respectively have a second taper on the inner surface of the contact hole, the second taper inclines at a second angle with respect to the surface of the semiconductor substrate, and

the second angle is greater than the first angle.

4. The device of claim 2 , wherein the two upper layers respectively have a first taper on the inner surface of the contact hole, the first taper inclines at a first angle with respect to the surface of the semiconductor substrate,

the two lower layers respectively have a second taper on the inner surface of the contact hole, the second taper inclines at a second angle with respect to the surface of the semiconductor substrate, and

the second angle is greater than the first angle.

5. The device of claim 3 , wherein the first angle is equal to or smaller than 86 degrees.

6. The device of claim 3 , wherein the first angle is equal to or smaller than 85 degrees.

7. The device of claim 1 , wherein in the stacked structure, a first layer closest to the lower-layer wiring is a porous film, a second layer on the first layer is an oxide film, a third layer on the second layer is a nitride film, and a fourth layer on the third layer is an oxide film.

8. The device of claim 7 , wherein when a dielectric constant of the first layer is E41, a dielectric constant of the second layer is E42, a dielectric constant of the third layer is E43, and a dielectric constant of the fourth layer is E44, the dielectric constants E41, E42, E43, and E44 satisfy an expression 1

E44<E43, E42<E43, and E42>E41  (Expression 1).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2013
From: INABA, MERII; HIZAWA, TAKESHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 030374/0770 →
Priority Claims (1)
JP 2012-195167 · Sep 5, 2012 · national
Continuity (1)
Related Publication 20140061929A1 · Mar 6, 2014