Three-dimensional quantum well transistor and fabrication method
View Patent ↗Three dimensional quantum well transistors and fabrication methods are provided. A quantum well layer, a barrier layer, and a gate structure can be sequentially formed on an insulating surface of a fin part. The gate structure can be formed over the barrier layer and across the fin part. The QW layer and the barrier layer can form a hetero-junction of the transistor. A recess can be formed in the fin part on both sides of the gate structure to suspend a sidewall spacer. A source and a drain can be formed by growing an epitaxial material in the recess and the sidewall spacer formed on both sidewalls of the gate electrode can be positioned on surface of the source and the drain.
1. A method for forming a transistor comprising:
providing a semiconductor substrate;
forming a buffer layer on the semiconductor substrate;
forming a fin part by etching the buffer layer, wherein the fin part is formed of an insulating material;
forming an insulating layer on the semiconductor substrate, the insulating layer having a top surface lower than a top surface of the fin part;
forming a quantum well (QW) layer on surface of the fin part;
forming a barrier layer on surface of the QW layer;
forming a gate structure on the barrier layer across the fin part and on the insulating layer, the gate structure including a gate dielectric layer on each of the insulating layer and the barrier layer, and a gate electrode on the gate dielectric layer;
forming a sidewall spacer on both sidewalls of the gate structure;
forming a recess in the fin part on both sides of the gate structure to suspend the sidewall spacer; and
forming a source and a drain by growing an epitaxial material in the recess, each of the source and the drain including a side edge aligned with a sidewall edge of the gate structure such that a channel region in the QW layer under the gate structure having a same width with the gate structure and the channel region does not extend to under the sidewall spacer.
2. The method according to claim 1 , where forming the recess to suspend the sidewall spacer includes:
using the gate structure and the sidewall spacer as a mask to dry etch the barrier layer, the QW layer, and the fin part; and
using a wet etching process to remove a portion of each of the barrier layer, the QW layer, and the fin part, under the sidewall spacer to suspend the sidewall spacer.
3. The method according to claim 1 , wherein the buffer layer is formed on a crystal plane (111) of the semiconductor substrate.
4. The method according to claim 1 , wherein the buffer layer is made of a material including AlN, and the buffer layer has a thickness ranging from about 1 micron to 2 microns.
5. The method according to claim 1 , wherein the QW layer is made of a material including a compound selected from group III-V and group II-VI.
6. The method according to claim 1 , wherein the QW layer is made of a material including GaN, AlGaN, InGaN, or Ge, and the QW layer has a thickness ranging from about 10 nm to 100 nm.
7. The method according to claim 1 , wherein the barrier layer is made of a material including a compound selected from group III-V and group II-VI.
8. The method according to claim 1 , wherein the barrier layer is made of a material including AlN, AlGaN, or AlInN, and the barrier layer has a thickness ranging from about 1 nm to 10 nm.
9. The method according to claim 1 , wherein, prior to forming the gate structure, a capping layer is formed on the barrier layer, and wherein the capping layer has a thickness ranging from about 1 nm to 3 nm and is made of a material including GaN.
10. The method according to claim 1 , wherein each of the source and the drain is made of a material including N-doped GaN.
11. The method according to claim 1 , further including forming a metal electrode on each of the source and the drain, wherein the metal electrode is made of a material including NiAu or CrAu.