IP Library Granted Patent US 9,029,688
Granted Patent B2
US 9,029,688 · App. 13/071,074 · Granted May 12, 2015

Photovoltaic device including flexible substrate or inflexible substrate and method for manufacturing the same

Inventor: Seung-Yeop Myong (Seoul, KR)
Assignee: Intellectual Discovery Co., Ltd.
H01L31/03529H01L31/02363H01L31/03685H01L31/03687H01L31/076H01L31/03845H01L31/03926Y02E10/52Y02E10/545Y02E10/548
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,029,688
App. No.
13/071,074
Granted
May 12, 2015
Kind
B2
Abstract

Disclosed is a photovoltaic device. The photovoltaic device includes: a substrate; a first electrode placed on the substrate; a second electrode which is placed opposite to the first electrode and which light is incident on; a first unit cell being placed between the first electrode and the second electrode, and including an intrinsic semiconductor layer including crystalline silicon grains making the surface of the intrinsic semiconductor layer toward the second electrode textured; and a second unit cell placed between the first unit cell and the second electrode.

Claims (14)

1. A method for manufacturing an n-i-p type photovoltaic device including a first unit cell and a second unit cell on which light is incident, the method comprising:

forming an n-type semiconductor layer of the first unit cell on a substrate;

forming an intrinsic semiconductor layer of the first unit cell on the n-type semiconductor layer, the intrinsic semiconductor layer comprising a mixed phase hydrogenated microcrystalline silicon based material comprising an amorphous silicon based material and crystalline silicon grains;

etching a surface of the intrinsic semiconductor layer to partially expose the silicon grains, such that the intrinsic semiconductor layer has a first surface that is textured by the exposed silicon grains and a non-textured opposing second surface; and

forming a p-type semiconductor layer of the first unit cell on the intrinsic semiconductor layer,

wherein an average crystal volume fraction of the intrinsic semiconductor layer of the first unit cell ranges from 25% to 75%.

2. The method of claim 1 , wherein the substrate is a flexible substrate.

3. The method of claim 1 , wherein the etching the surface of the intrinsic semiconductor layer is performed by a dry-etching process.

4. The method of claim 3 , wherein the dry-etching process is a hydrogen plasma etching process or an argon plasma etching process.

5. The method of claim 1 , wherein the amorphous silicon based material is etched more quickly than the crystalline silicon grain.

6. The method of claim 1 wherein a passivation layer is formed on the etched surface of the intrinsic semiconductor layer.

7. The method of claim 6 , wherein the passivation layer comprises a hydrogenated microcrystalline silicon based material.

8. The method of claim 1 , further comprising forming an electrode on the second unit cell,

wherein an average pitch of a textured surface of the electrode is equal to or more than 50 nm and equal to or less than 500 nm.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2013
From: KISCO
To: INTELLECTUAL DISCOVERY CO., LTD.
Reel/Frame 030735/0841 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2011
From: MYONG, SEUNG-YEOP
To: KISCO
Reel/Frame 026320/0860 →
Priority Claims (1)
KR 10-2010-0027280 · Mar 26, 2010 · national
Continuity (1)
Related Publication 20110232732A1 · Sep 29, 2011