Semiconductor device having a fuse
A semiconductor device comprises an active region including a core circuit forming region and a buffer forming region, and a fuse element forming region arranged on a corner of the active region and to be able to be electrically fused. It is possible to arrange the fuse element without forming the fuse in the core circuit forming region by arranging the fuse element forming region at the corner of the active region.
1. A semiconductor device comprising:
a chip;
a SRAM formed on the chip;
an active region including a core circuit forming region and a buffer forming region on the chip;
a fuse element forming region arranged on a corner of the active region and including a fuse element able to be electrically fused; and
a pad forming region arranged around the buffer forming region and outside of the active region,
wherein the active region, the fuse element and the pad forming region are arranged on the chip, the fuse element region being arranged within the active region,
the fuse element is coupled to the SRAM,
the fuse element is coupled to a first pad and a second pad in the pad forming region,
the first pad is opened to an external terminal, and
the second pad is bonded to the external terminal by a wire bonding.
2. The semiconductor device according to claim 1 ,
wherein the first pad and the second pad are formed near the corner of the active region.
3. The semiconductor device according to claim 1 ,
wherein the first pad is arranged closer to a corner of the chip than the second pad,
the corner of the chip is closest corner from the fuse element.
4. The semiconductor device according to claim 1 , further comprising:
a wire for fusing connected to said fuse element,
the wire for fusing being formed in several wire layers arranged in an upper layer of the corner of the chip.
5. The semiconductor device according to claim 1 , further comprising:
a first group of buffers being arranged within said buffer forming region and along a first direction parallel to first side of the chip; and
a second group of buffers being arranged within said buffer forming region and along a second direction intersect with the first direction and parallel to second side of the chip,
wherein the fuse element is formed between the first group of buffers and the second group of buffers.
6. The semiconductor device according to claim 1 , wherein the fuse element is connected to the first pad and the second pad by a common wiring.
7. A semiconductor device comprising:
a chip;
a SRAM formed on the chip; and
a fuse element arranged on the chip and able to be electrically fused,
wherein the fuse element is coupled to the SRAM,
the fuse element is coupled to a first pad and a second pad,
the first pad is opened to an external terminal, and
the second pad is bonded to the external terminal by a wire bonding,
and wherein the fuse element and the SRAM are located within an active region of the chip, and the first and second pads are located outside of said active region.
8. The semiconductor device according to claim 7 ,
wherein the first pad and the second pad are formed near the corner of the chip.
9. The semiconductor device according to claim 7 ,
wherein the first pad is arranged closer to a corner of the chip than the second pad,
the corner of the chip is closest corner from the fuse element.
10. The semiconductor device according to claim 7 , further comprising:
a wire for fusing connected to the fuse element,
wherein the wire for fusing being formed in several wire layers arranged in an upper layer of a corner of the chip.
11. The semiconductor device according to claim 7 , further comprising:
a first group of buffers being arranged to first direction parallel to first side of the chip; and
a second group of buffers being arranged to second direction intersect with the first direction and parallel to second side of the chip die,
wherein the fuse element is formed between the first group of buffers and the second group of buffers.
12. The semiconductor device according to claim 7 , wherein the fuse element is connected to the first pad and the second pad by a common wiring.
13. A semiconductor device comprising:
a chip;
a first group of pads being arranged to first direction parallel to first side of the chip;
a second group of pads being arranged to second direction intersect with the first direction and parallel to second side of the chip; and
a fuse macro including a fuse element,
wherein the fuse macro arranged on the chip and to be able to be electrically fused;
the fuse macro is coupled to a first pad, a second pad and a third pad,
the first pad and the second pad belong to the first group of pads and the third pad belongs to the second group of pads,
the first pad is opened to an external terminal,
and
the second pad is bonded to the external terminal by a wire bonding.
14. The semiconductor device according to claim 13 ,
wherein the fuse element is coupled to the first pad and the second pad.
15. The semiconductor device according to claim 13 ,
wherein the first pad is arranged closer to a corner of the chip than the second pad,
the corner of the chip is closest corner from the fuse element.
16. The semiconductor device according to claim 13 , further comprising:
a wire for fusing connected to the fuse macro,
wherein the wire for fusing being formed in several wire layers arranged in an upper layer of a corner of the chip.
17. The semiconductor device according to claim 13 , further comprising:
a first group of buffers being arranged to first direction parallel to first side of the chip; and
a second group of buffers being arranged to second direction intersect with the first direction and parallel to second side of the chip die,
wherein the fuse macro is formed between the first group of buffers and the second group of buffers.
18. A semiconductor device comprising:
a chip;
a SRAM;
a fuse element arranged on the chip and able to be electrically fused; and
a wire for fusing connected to the fuse element,
wherein the fuse element is coupled to the SRAM,
wherein the wire for fusing is also connected to a first pad and a second pad, the fuse element being disposed in an active region of the chip and the first and second pads being disposed in a peripheral region of the chip that is outside of the active region, and
the wire for fusing being formed in several wire layers arranged in an upper layer of a corner region of the chip.
19. The semiconductor device according to claim 18 ,
wherein the fuse element is coupled to a first pad and a second pad,
the first pad and the second pad are formed near the corner of the chip.
20. The semiconductor device according to claim 18 ,
wherein the fuse element is coupled to a first pad and a second pad,
the first pad is arranged closer to a corner of the chip than the second pad,
the corner of the chip is closest corner from the fuse element.
21. The semiconductor device according to claim 18 ,
wherein the fuse element is coupled to a first pad and a second pad,
the first pad is opened to an external terminal, and
the second pad is bonded to the external terminal by a wire bonding.
22. The semiconductor device according to claim 18 , further comprising:
a first group of buffers being arranged to first direction parallel to first side of the chip; and
a second group of buffers being arranged to second direction intersect with the first direction and parallel to second side of the chip,
wherein the fuse element is formed between the first group of buffers and the second group of buffers.
23. The semiconductor device according to claim 18 , wherein the corner region is within the active region.