Multiprocessor system, multiprocessor control method, and multiprocessor integrated circuit

1. A multiprocessor system comprising:

a processor array composed of three or more processors that are arranged in a matrix and communicating with each other, wherein each pair of adjacent processors in the matrix are connected to each other such that the adjacent processors can communicate with each other without performing a routing process for any other processors in the matrix, and each respective processor of the three or more processors in the matrix is connected to a processor that is not adjacent to the respective processor such that the respective processor and the processor that is not adjacent to the respective processor can communicate with each other by performing a routing process for at least one of the processors that are adjacent to the respective processor; and

a task management unit operable to select three or more of said processors of the processor array as respective three or more task-assigned processors for processing a group of tasks, and determine an amount of tasks to be assigned to each of the said task-assigned processors based on a number of processors adjacent in the matrix to that task-assigned processor, wherein

the three or more task-assigned processors includes a first task-assigned processor and a second task-assigned processor,

the task management unit determines the amount of tasks to be assigned to each of said task-assigned processors based on a number of adjacent task-assigned processors in the matrix to the respective said task-assigned processors, wherein an amount of tasks assigned to the first task-assigned processor is larger than an amount of tasks assigned to the second task-assigned processor when a number of task-assigned processors adjacent in the matrix to the first task-assigned processor is greater than a number of task-assigned processors adjacent in the matrix to the second task-assigned processor, and

the task management unit assigns tasks to each of said task-assigned processors according to the determining.

2. The multiprocessor system of claim 1 , further comprising:

an operating frequency determining unit operable to determine an operating frequency of each processor in accordance with the amount of tasks assigned to each processor by the task management unit; and

an operation control unit operable to cause each processor to operate at the operating frequency determined by the operating frequency determining unit, wherein

the operating frequency determining unit determines operating frequencies such that an operating frequency of the first task-assigned processor is equal to or higher than an operating frequency of the second task-assigned processor.

3. The multiprocessor system of claim 2 , further comprising:

an operating voltage determining unit operable to, when it is found, based on the operating frequencies determined by the operating frequency determining unit, that there are a processor operating at the first operating frequency and a processor operating at the second operating frequency which is lower than the first operating frequency, determine operating voltages of each processor such that an operating voltage of the processor operating at the first operating frequency is equal to or higher than an operating voltage of the processor operating at the second operating frequency; and

a voltage supply unit operable to supply the operating voltages determined by the operating voltage determining unit to each processor.

4. The multiprocessor system of claim 2 , wherein

the operating frequency determining unit determines the operating frequencies such that, when there is a processor to which no task is assigned, an operating frequency of the processor to which no task is assigned is 0 hertz.

5. The multiprocessor system of claim 1 , further comprising:

a storage unit storing connection information reflecting connection relationships between processors, wherein

the task management unit assigns tasks, which are to be processed by the processors, to the processors by referring to the connection information stored in the storage unit.

6. The multiprocessor system of claim 1 , wherein:

in a predetermined case, the task management unit determines the amount of tasks to be assigned such that a processor that currently has the largest amount of tasks is not to be assigned as the processor having the largest amount of tasks when the tasks are assigned next.

7. The multiprocessor system of claim 6 , wherein:

the predetermined case is a case where a predetermined time is passed.

8. The multiprocessor system of claim 6 , wherein:

the predetermined case is a case when a change in number of processing-target tasks is detected.

9. The multiprocessor system of claim 1 , wherein:

the task management unit selects the three or more task-assigned processors such that at least two of the task-assigned processors are processors that are directly connected to each other.

10. The multiprocessor system of claim 1 , wherein:

the amount of tasks is the number of tasks.

11. The multiprocessor system of claim 1 , wherein:

all processors included in the multiprocessor system have the same shape and are arranged in a matrix in at least one semiconductor integrated circuit.

12. The multiprocessor system of claim 1 , wherein:

all processors included in the multiprocessor system are arranged in a three-dimensional manner.

13. A multiprocessor control method for controlling a multiprocessor system including a processor array composed of three or more processors that are arranged in a matrix and communicating with each other, wherein each pair of adjacent processors in the matrix are connected to each other such that the adjacent processors can communicate with each other without performing a routing process for any other processors in the matrix, and each respective processor of the three or more processors in the matrix is connected to a processor that is not adjacent to the respective processor such that the respective processor and the processor that is not adjacent to the respective processor can communicate with each other by performing a routing process for at least one of the processors that are adjacent to the respective processor; and a task management unit, said method comprising:

selecting, by the task management unit, three or more of the processors of the processor array as respective three or more task-assigned processors for processing a group of tasks, and

determining, by the task management unit, an amount of tasks to be assigned to each of said task-assigned processors based on a number of processors adjacent in the matrix to that task-assigned processor,

wherein the three or more task-assigned processors includes a first task-assigned processor and a second task-assigned processor,

wherein said determining of the amount of tasks to be assigned to each of said task-assigned processors is performed based on a number of adjacent task-assigned processors in the matrix to the respective said task-assigned processors, wherein an amount of tasks assigned to the first task-assigned processor is larger than an amount of tasks assigned to the second task-assigned processor when a number of task-assigned processors adjacent in the matrix to the first task-assigned processor is greater than a number of task-assigned processors adjacent in the matrix to the second task-assigned processor, and

assigning, by the task management unit, tasks to each of said task-assigned processors according to said determining.

14. A multiprocessor integrated circuit comprising:

a processor array composed of three or more processors that are arranged in a matrix and communicating with each other, wherein each pair of adjacent processors in the matrix are connected to each other such that the adjacent processors can communicate with each other without performing a routing process for any other processors in the matrix, and each respective processor of the three or more processors in the matrix is connected to a processor that is not adjacent to the respective processor such that the respective processor and the processor that is not adjacent to the respective processor can communicate with each other by performing a routing process for at least one of the processors that are adjacent to the respective processor; and

a task management unit operable to select three or more of said processors of the processor array as respective three or more task-assigned processors for processing a group of tasks, and determine an amount of tasks to be assigned to each of said task-assigned processors based on a number of processors adjacent in the matrix to that task-assigned processor, wherein

the three or more task-assigned processors includes a first task-assigned processor and a second task-assigned processor,

the task management unit determines the amount of tasks to be assigned to each of said task-assigned processors based on a number of adjacent task-assigned processors in the matrix to the respective said task-assigned processors, wherein an amount of tasks assigned to the first task-assigned processor is larger than an amount of tasks assigned to the second task-assigned processor when a number of task-assigned processors adjacent in the matrix to the first task-assigned processor is greater than a number of task-assigned processors adjacent in the matrix to the second task-assigned processor, and

the task management unit assigns tasks to each of said task-assigned processors according to the determining.