Structure and method for determining a defect in integrated circuit manufacturing process
The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas.
1. A method for determining a manufacturing defect in integrated circuit manufacturing process, comprising:
providing a plurality of normal active areas on a sample;
placing a plurality of defective active areas on said sample, wherein said normal active areas and said defective active areas are interlaced;
obtaining a charge particle microscope image of said sample; and
determining said manufacturing defect on said sample from said charged particle microscope image.
2. The method for determining a manufacturing defect of claim 1 , wherein said manufacturing defect is a void-induced short of said normal active areas.
3. The method for determining a manufacturing defect of claim 2 , wherein said void-induced short is determined by monitoring the bright voltage contrast image of said active areas from said charged particle microscope image.
4. The method for determining a manufacturing defect of claim 1 , wherein said defect is a non-open contact of said normal active areas.
5. The method for determining a manufacturing defect of claim 4 , wherein said non-open contact is determined by monitoring the dark voltage contrast image of said active areas that has large voltage contrast difference from said charged particle microscope image.
6. The method for determining a manufacturing defect of claim 1 , wherein said sample comprises a dynamic random access memory.
7. The method for determining a manufacturing defect of claim 1 , wherein said active areas are active areas of semiconductor devices.
8. The method for determining a manufacturing defect of claim 7 , wherein said normal active areas are active areas of semiconductor devices having heavily n-type doped source and drain, and p-type doped well (N+/P-well).
9. The method for determining a manufacturing defect of claim 7 , wherein said defective active areas are active areas of semiconductor devices having heavily p-type doped source and drain, and p-type doped well (P+/P-well).
10. The method for determining a manufacturing defect of claim 7 , wherein said defective active areas are active areas of semiconductor devices having heavily n-type doped source and drain, and n-type doped welt (N+/N-well).