Circuit and method for initializing a computer system

1. A circuit for use in a computing system comprising:

an autoload controller having an input to receive an initialization signal;

a bus interface unit coupled to the autoload controller for accessing an external memory; and

wherein the autoload controller, in response to receiving the initialization signal, searches for a signature by reading an address location related to a memory size for each of a plurality of memory sizes to determine a size of the external memory until the signature is found using the bus interface unit, wherein the signature comprises a unique digital code, and in response to finding the signature at a signature address, loads a plurality of base addresses corresponding to a plurality of controllers from memory locations having a predetermined relationship to the signature address.

2. The circuit of claim 1 , wherein the autoload controller provides the plurality of base addresses to a control output thereof, in response to loading the plurality of base address.

3. The circuit of claim 1 , further comprising:

a remapping circuit responsive to an input address for remapping the input address to a remapped address using a base address of the plurality of base addresses corresponding to a source of the input address.

4. The circuit of claim 3 , wherein the remapping circuit stores the plurality of base addresses.

5. The circuit of claim 1 , further comprising a southbridge comprising the autoload controller and the bus interface unit.

6. The circuit of claim 5 , further comprising:

a northbridge coupled to the southbridge; and

a processing unit coupled to the northbridge.

7. The circuit of claim 6 , wherein the processing unit comprises a central processing unit.

8. The circuit of claim 6 , wherein the processing unit comprises a graphics processing unit.

9. The circuit of claim 6 , wherein the signature address is located within a memory space allocated to a basic input/output system (BIOS).

10. The circuit of claim 1 , wherein a bottom address is defined by the memory size and the address location is offset by a predetermined offset from the bottom address.

11. The circuit of claim 1 , wherein each of the plurality of memory sizes is equal to a power of two.

12. The circuit of claim 1 , wherein each of the plurality of base addresses indicates a memory block containing firmware for a corresponding controller of the plurality of controllers.

13. An integrated circuit comprising:

an internal bus;

a bus bridge having a first port coupled to a first plurality of external terminals, and a second port coupled to the internal bus;

a bus interface unit having a first port, and a second port coupled to a second plurality of external terminals, the bus interface unit for accessing an external memory over the second port;

a remapping circuit having an input for receiving an input address, and an output for providing a remapped address to the first port of the bus interface unit;

an autoload controller coupled to the remapping circuit, the internal bus and the bus interface unit and having an input for receiving an initialization signal; and

wherein the autoload controller, in response to receiving the initialization signal, searches for a signature using the bus interface unit, wherein the signature comprises a unique digital code, and in response to finding the signature at a signature address, provides each of a plurality of base addresses from memory locations having a predetermined relationship to the signature address to the remapping circuit; and

wherein the autoload controller searches for the signature by reading an address location offset by a predetermined offset from a first starting address defining a first memory size of the external memory, and if the address location does not contain the signature, reading further address locations offset by the predetermined offset from each of a plurality of starting addresses defining corresponding memory sizes until the signature is found.

14. The integrated circuit of claim 13 , wherein the integrated circuit generates the initialization signal in response to a power state transition.

15. The integrated circuit of claim 13 , wherein autoload controller searches for the signature using a flash controller.

16. The integrated circuit of claim 13 , further comprising:

a flash controller coupled to the autoload controller and the remapping circuit.

17. A method comprising:

searching a signature address for a signature in response to receiving an initialization signal using a bus interface unit of a computer system, wherein the signature comprises a unique digital code, wherein the searching comprises searching for the signature at an address location offset by a predetermined offset from a first starting address defining a first memory size of an external memory, and if the address location does not contain the signature, reading further address locations offset by the predetermined offset from each of a plurality of starting addresses defining corresponding memory sizes of the external memory until the signature is found; and

reading a first base address indicating a first location of firmware for a first controller in response to finding the signature, the first base address having a predetermined relationship to the signature address.

18. The method of claim 17 further comprising:

remapping an input address using the first base address to provide a remapped address.

19. The method of claim 17 , further comprises:

reading a second base address indicating a second location of firmware for a second controller, the second base address having a second predetermined relationship to the signature address.

20. The method of claim 17 , wherein the searching further comprises:

comparing a first value stored at the signature address to a predetermined value; and

finding the signature at the signature address if the first value equals the predetermined value.

21. The method of claim 17 , wherein the memory sizes are powers of two.