Semiconductor integrated circuit
Disclosed herein is a semiconductor integrated circuit including: a cell layout region including circuit cells subject to power control the supply and interruption of power to which is controlled by a power switch, and always-on circuit cell groups which are always powered after the activation; a main line laid out in the cell layout region and applied with a source or reference voltage; and first and second branch lines which branch from the main line in the cell layout region.
1. A semiconductor integrated circuit comprising:
a power switch configured to provide electrical connection and disconnection between a first branch line and a main line, said main line extending along a first direction;
a peripheral circuit cell electrically connected to said first branch line, said first branch line extending along a second direction;
a branch connection circuit cell electrically connected to a second branch line, said second branch line extending along said second direction;
an individual connection circuit cell electrically connected to an individual connection line, said individual connection line being electrically connected to said main line,
wherein said individual connection line is shorter than said first branch line, said individual connection line being shorter than said second branch line,
wherein said first branch line is in a first wiring layer and said second branch line is in a second wiring layer, said second wiring layer being between said first wiring layer and said main line.
2. The semiconductor integrated circuit of claim 1 , wherein said second direction differs from said first direction.
3. The semiconductor integrated circuit of claim 1 , wherein said second direction is orthogonal to said first direction.
4. The semiconductor integrated circuit of claim 1 , wherein said peripheral circuit cell is directly electrically connected to said first branch line.
5. The semiconductor integrated circuit of claim 1 , wherein said branch connection circuit cell is directly electrically connected to said second branch line.
6. The semiconductor integrated circuit of claim 1 , wherein said second branch line is directly electrically connected to said main line.
7. The semiconductor integrated circuit of claim 1 , wherein said individual connection circuit cell is directly electrically connected to said individual connection line.
8. The semiconductor integrated circuit of claim 1 , wherein said individual connection line is directly electrically connected to said main line.
9. The semiconductor integrated circuit of claim 1 , wherein a source current driving capability of the individual connection circuit cell higher than a source current driving capability of the branch connection circuit cell.
10. The semiconductor integrated circuit of claim 1 , wherein a total transistor gate width of the individual connection circuit cell is greater than a total transistor gate width of the branch connection circuit cell.
11. The semiconductor integrated circuit of claim 1 , wherein said individual connection circuit cell is between said peripheral circuit cell and said main line.
12. The semiconductor integrated circuit of claim 1 , wherein said peripheral circuit cell is between said branch connection circuit cell and said main line.
13. The semiconductor integrated circuit of claim 1 , wherein said peripheral circuit cell and said individual connection circuit cell are disposed within a predetermined distance from the main line.
14. The semiconductor integrated circuit of claim 1 , wherein a maximum source current capable of flowing through the individual connection circuit cell is greater than a maximum source current capable of flowing through the branch connection circuit cell.
15. The semiconductor integrated circuit of claim 1 , wherein said power switch is configured to electrically connect said first branch line to said main line.
16. The semiconductor integrated circuit of claim 1 , wherein said power switch is configured to disconnect said first branch line from said main line.
17. The semiconductor integrated circuit of claim 1 , wherein said main line is configure to receive a source or reference voltage.
18. The semiconductor integrated circuit of claim 1 , wherein said main line is in parallel with a different main line, said different main line being spaced apart from said main line.
19. The semiconductor integrated circuit of claim 1 , wherein said branch connection circuit cell is configured to remain powered.
20. The semiconductor integrated circuit of claim 1 , wherein said individual connection circuit cell is configured to remain powered.