IP Library Granted Patent US 9,048,323
Granted Patent B2
US 9,048,323 · App. 13/868,420 · Granted Jun 2, 2015

Semiconductor device

Inventors: Shunpei Yamazaki (Tokyo, JP); Hideomi Suzawa (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/7869H01L29/78648
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Quick Facts
Patent No.
US 9,048,323
App. No.
13/868,420
Granted
Jun 2, 2015
Kind
B2
Abstract

A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.

Claims (45)

1. A semiconductor device comprising:

an oxide semiconductor layer;

a first conductive film over and in contact with the oxide semiconductor layer;

a second conductive film over and in contact with the oxide semiconductor layer;

a first insulating layer over the first conductive film and the second conductive film, the first insulating layer comprising an opening overlapping with a first region of the oxide semiconductor layer;

a second insulating layer over the first insulating layer, the second insulating layer being in contact with the first region of the oxide semiconductor layer; and

a gate electrode layer over the second insulating layer, the gate electrode layer overlapping with the oxide semiconductor layer, the first conductive film, and the second conductive film,

wherein each of the first conductive film and the second conductive film comprises a region projecting in a channel length direction, at a lower end portion,

wherein the region of the first conductive film, the gate electrode layer, and the oxide semiconductor layer overlap with each other,

wherein the region of the second conductive film, the gate electrode layer, and the oxide semiconductor layer overlap with each other,

wherein a width of the opening of the first insulating layer in the channel length direction is larger than a distance between the first conductive film and the second conductive film and smaller than a width of the gate electrode layer in the channel length direction, and

wherein a width of the opening of the first insulating layer in a channel width direction is smaller than a width of the first conductive film in the channel width direction.

2. The semiconductor device according to claim 1 ,

wherein a second region of the oxide semiconductor layer is in contact with the first conductive film,

wherein a thickness of the first region of the oxide semiconductor layer is smaller than a thickness of the second region of the oxide semiconductor layer.

3. The semiconductor device according to claim 1 , further comprising an oxide insulating layer below and in contact with the oxide semiconductor layer, the oxide insulating layer comprising at least one of metal elements selected from constituent elements of the oxide semiconductor layer.

4. The semiconductor device according to claim 3 , wherein the oxide insulating layer comprises gallium oxide.

5. The semiconductor device according to claim 3 , further comprising a conductive layer below the oxide insulating layer,

wherein the conductive layer and the oxide semiconductor layer overlap with each other.

6. The semiconductor device according to claim 1 , wherein the second insulating layer comprises at least one of metal elements selected from constituent elements of the oxide semiconductor layer.

7. An electronic device comprising the semiconductor device according to claim 1 .

8. A semiconductor device comprising:

a transistor comprising a channel formation region comprising silicon;

a first insulating layer over the transistor;

an oxide semiconductor layer;

a first conductive film over and in contact with the oxide semiconductor layer;

a second conductive film over and in contact with the oxide semiconductor layer;

a second insulating layer over the first conductive film and the second conductive film, the second insulating layer comprising an opening overlapping with a first region of the oxide semiconductor layer;

a third insulating layer over the second insulating layer, the third insulating layer being in contact with the first region of the oxide semiconductor layer; and

a gate electrode layer over the third insulating layer, the gate electrode layer overlapping with the oxide semiconductor layer, the first conductive film, and the second conductive film,

wherein a gate of the transistor is electrically connected to the first conductive film,

wherein each of the first conductive film and the second conductive film comprises a region projecting in a channel length direction, at a lower end portion,

wherein the region of the first conductive film, the gate electrode layer, and the oxide semiconductor layer overlap with each other,

wherein the region of the second conductive film, the gate electrode layer, and the oxide semiconductor layer overlap with each other,

wherein a width of the opening of the second insulating layer in the channel length direction is larger than a distance between the first conductive film and the second conductive film and smaller than a width of the gate electrode layer in the channel length direction, and

wherein a width of the opening of the second insulating layer in a channel width direction is smaller than a width of the first conductive film in the channel width direction.

9. The semiconductor device according to claim 8 ,

wherein a second region of the oxide semiconductor layer is in contact with the first conductive film,

wherein a thickness of the first region of the oxide semiconductor layer is smaller than a thickness of the second region of the oxide semiconductor layer.

10. The semiconductor device according to claim 8 , further comprising an oxide insulating layer below and in contact with the oxide semiconductor layer, the oxide insulating layer comprising at least one of metal elements selected from constituent elements of the oxide semiconductor layer.

11. The semiconductor device according to claim 10 , wherein the oxide insulating layer comprises gallium oxide.

12. The semiconductor device according to claim 10 , further comprising a conductive layer below the oxide insulating layer,

wherein the conductive layer and the oxide semiconductor layer overlap with each other.

13. The semiconductor device according to claim 8 , wherein the third insulating layer comprises at least one of metal elements selected from constituent elements of the oxide semiconductor layer.

14. An electronic device comprising the semiconductor device according to claim 8 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 30, 2013
From: YAMAZAKI, SHUNPEI; SUZAWA, HIDEOMI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 030321/0958 →
Priority Claims (1)
JP 2012-104286 · Apr 30, 2012 · national
Continuity (1)
Related Publication 20130285050A1 · Oct 31, 2013