Three-dimensional gate-wrap-around field-effect transistor
View Patent ↗A three-dimensional Gate-Wrap-Around Field-Effect Transistor (GWAFET). The GWAFET includes a substrate of III-V semiconductor material. The GWAFET further includes one or more channel layers with a gate wrapped around these one or more channel layers. Additionally, the GWAFET includes a barrier layer residing on the top channel layer with a layer of doped III-V semiconductor material residing on each end of the barrier layer. A source and drain contact are connected to the layer of doped III-V semiconductor material as well as to the multiple channels in the embodiment with the GWAFET including multiple channel layers. By having such a structure, integration density is improved. Furthermore, electrostatic control is improved due to gate coupling, which helps reduce standby power consumption. Furthermore, by using III-V semiconductor material as opposed to silicon, the current drive capacity is improved.
1. A semiconductor device, comprising:
a substrate comprising III-V semiconductor material;
a channel layer comprising III-V semiconductor material;
a gate wrapped around said channel layer, wherein said gate is in direct contact with said channel layer and said substrate;
a barrier layer residing on said channel layer;
a layer of doped III-V semiconductor material residing on each end of said barrier layer;
a source contact connected to a first end of said layer of doped III-V semiconductor material; and
a drain contact connected to a second end of said layer of doped III-V semiconductor material.
2. The semiconductor device as recited in claim 1 further comprising:
a buffer layer in contact with a portion of said gate, wherein said buffer layer separates said channel layer and said substrate.
3. The semiconductor device as recited in claim 2 , wherein said buffer layer comprises indium phosphide.
4. The semiconductor device as recited in claim 2 , wherein a thickness of said buffer layer is approximately 500 nm.
5. The semiconductor device as recited in claim 1 further comprising:
a barrier layer separating said channel layer and said layer of doped III-V semiconductor material.
6. The semiconductor device as recited in claim 5 , wherein said barrier layer comprises indium phosphide.
7. The semiconductor device as recited in claim 5 , wherein a thickness of said barrier layer is approximately 1 nm.
8. The semiconductor device as recited in claim 1 , wherein said channel layer comprises indium gallium arsenide.
9. The semiconductor device as recited in claim 1 , wherein a thickness of said channel layer is approximately 50 nm.
10. The semiconductor device as recited in claim 1 further comprising:
a layer of aluminum oxide separating said channel layer and said gate.
11. The semiconductor device as recited in claim 1 , wherein said substrate comprises semi-insulating indium phosphide.
12. A semiconductor device, comprising:
a substrate comprising III-V semiconductor material;
a plurality of alternating channel and buffer layers, where each of said alternating channel and buffer layers comprises III-V semiconductor material;
a gate wrapped around said alternating channel layers, wherein said gate is in direct contact with each of said channel layers and said substrate;
a barrier layer residing on a top channel layer of said channel layers;
a layer of doped III-V semiconductor material residing on each end of said barrier layer;
a source contact connected to said plurality of channel layers, said barrier layer and a first end of said layer of doped III-V semiconductor material; and
a drain contact connected to said plurality of channel layers, said barrier layer and a second end of said layer of doped III-V semiconductor material.
13. The semiconductor device as recited in claim 12 further comprising:
a layer of aluminum oxide separating said channel layers and said gate.
14. The semiconductor device as recited in claim 12 , wherein said channel layers comprise indium gallium arsenide.
15. The semiconductor device as recited in claim 12 , wherein said barrier layer separates said top channel layer of said channel layers and said layer of doped III-V semiconductor material, wherein said barrier layer comprises III-V semiconductor material.
16. The semiconductor device as recited in claim 12 , wherein said buffer layers comprise indium phosphide.
17. The semiconductor device as recited in claim 12 , wherein a first buffer layer of said buffer layers in contact with said substrate comprises undoped III-V semiconductor material, wherein the remaining buffer layers of said buffer layers comprise doped III-V semiconductor material.