Programmable logic device and semiconductor device
A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.
1. A programmable logic device comprising:
a plurality of programmable logic elements whose electrical connection is controlled by first configuration data, each of the programmable logic elements comprising:
a look-up table in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data,
a flip-flop to which the output signal of the look-up table is input, and
a multiplexer,
wherein the multiplexer includes at least two switches each including a first transistor and a second transistor,
wherein a gate of the second transistor is configured to be supplied with a signal including third configuration data through the first transistor,
wherein one of a source and a drain of the second transistor is configured to be supplied with the output signal of the look-up table or an output signal of the flip-flop, and
wherein the other of the source and the drain of the second transistor included in one of the two switches is electrically connected to the other of the source and the drain of the second transistor included in the other of the two switches.
2. The programmable logic device according to claim 1 ,
the look-up table comprising a plurality of logic gates, each of the logic gates comprising:
a plurality of third transistors for controlling electrical connection between a first wiring and a second wiring supplied with a first potential;
a plurality of fourth transistors for controlling electrical connection between the first wiring and a third wiring supplied with a second potential higher than the first potential;
a first node connected to one of a source and a drain of one of the plurality of third transistors and one of a source and a drain of another one of the plurality of third transistors;
a fifth transistor for controlling electrical connection with a fourth wiring supplied with a third potential higher than the first potential;
a second node connected to one of a source and a drain of one of the plurality of fourth transistors and one of a source and a drain of another one of the plurality of fourth transistors; and
a sixth transistor for controlling electrical connection with a fifth wiring supplied with a fourth potential lower than the third potential in accordance with a potential of the first wiring.
3. A semiconductor device comprising the programmable logic device according to claim 1 .
4. A display device comprising the programmable logic device according to claim 1 .
5. A light-emitting device comprising the programmable logic device according to claim 1 .
6. An electronic device comprising the programmable logic device according to claim 1 .
7. A programmable logic device comprising:
a plurality of programmable logic elements whose electrical connection is controlled by first configuration data, each of the programmable logic elements comprising:
a look-up table in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data,
a flip-flop to which the output signal of the look-up table is input, and
a multiplexer,
wherein the multiplexer includes at least two switches each including a first transistor and a second transistor,
wherein a gate of the second transistor is configured to be supplied with a signal including third configuration data through the first transistor,
wherein one of a source and a drain of the second transistor is configured to be supplied with the output signal of the look-up table or an output signal of the flip-flop,
wherein the other of the source and the drain of the second transistor included in one of the two switches is electrically connected to the other of the source and the drain of the second transistor included in the other of the two switches, and
wherein the first transistor includes a channel formation region in an oxide semiconductor film.
8. The programmable logic device according to claim 7 ,
the look-up table comprising a plurality of logic gates, each of the logic gates comprising:
a plurality of third transistors for controlling electrical connection between a first wiring and a second wiring supplied with a first potential;
a plurality of fourth transistors for controlling electrical connection between the first wiring and a third wiring supplied with a second potential higher than the first potential;
a first node connected to one of a source and a drain of one of the plurality of third transistors and one of a source and a drain of another one of the plurality of third transistors;
a fifth transistor for controlling electrical connection with a fourth wiring supplied with a third potential higher than the first potential;
a second node connected to one of a source and a drain of one of the plurality of fourth transistors and one of a source and a drain of another one of the plurality of fourth transistors; and
a sixth transistor for controlling electrical connection with a fifth wiring supplied with a fourth potential lower than the third potential in accordance with a potential of the first wiring.
9. A semiconductor device comprising the programmable logic device according to claim 7 .
10. A display device comprising the programmable logic device according to claim 7 .
11. A light-emitting device comprising the programmable logic device according to claim 7 .
12. An electronic device comprising the programmable logic device according to claim 7 .
13. A programmable logic device comprising:
a plurality of programmable logic elements whose electrical connection is controlled by first configuration data, each of the programmable logic elements comprising:
a look-up table in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data,
a flip-flop to which the output signal of the look-up table is input, and
a multiplexer,
wherein the multiplexer includes at least two switches each including a first transistor and a second transistor,
wherein a gate of the second transistor is configured to be supplied with a signal including third configuration data through the first transistor,
wherein one of a source and a drain of the second transistor is configured to be supplied with the output signal of the look-up table or an output signal of the flip-flop,
wherein the other of the source and the drain of the second transistor included in one of the two switches is electrically connected to the other of the source and the drain of the second transistor included in the other of the two switches,
wherein the first transistor includes a channel formation region in an oxide semiconductor film, and
wherein the oxide semiconductor film includes In, Ga, and Zn.
14. The programmable logic device according to claim 13 ,
the look-up table comprising a plurality of logic gates, each of the logic gates comprising:
a plurality of third transistors for controlling electrical connection between a first wiring and a second wiring supplied with a first potential;
a plurality of fourth transistors for controlling electrical connection between the first wiring and a third wiring supplied with a second potential higher than the first potential;
a first node connected to one of a source and a drain of one of the plurality of third transistors and one of a source and a drain of another one of the plurality of third transistors;
a fifth transistor for controlling electrical connection with a fourth wiring supplied with a third potential higher than the first potential;
a second node connected to one of a source and a drain of one of the plurality of fourth transistors and one of a source and a drain of another one of the plurality of fourth transistors; and
a sixth transistor for controlling electrical connection with a fifth wiring supplied with a fourth potential lower than the third potential in accordance with a potential of the first wiring.
15. A semiconductor device comprising the programmable logic device according to claim 13 .
16. A display device comprising the programmable logic device according to claim 13 .
17. A light-emitting device comprising the programmable logic device according to claim 13 .
18. An electronic device comprising the programmable logic device according to claim 13 .