Semiconductor device having vertical gates and fabrication thereof

1. A method for forming a semiconductor device with a vertical gate, comprising:

providing a substrate;

forming a recess in the substrate;

forming a gate dielectric layer on a sidewall and a bottom of the recess;

forming a polysilicon layer on the substrate;

after forming of the polysilicon layer on the substrate, forming source/drain regions in the polysilicon layer, wherein the substrate is separated from the source/drain regions by the gate dielectric layer;

forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer; and

forming a gate layer in the recess and on the adhesion layer.

2. The method for forming a semiconductor device with a vertical gate as claimed in claim 1 , wherein the metal of the metal silicide nitride layer is titanium, tantalum or tungsten.

3. The method for forming a semiconductor device with a vertical gate as claimed in claim 1 , wherein the gate layer comprises titanium nitride (TiN).

4. The method for forming a semiconductor device with a vertical gate as claimed in claim 1 , wherein steps of forming the recess in the substrate comprises:

forming a mask layer on the substrate;

patterning the mask layer with lithography and etching; and

etching the substrate using the mask layer as a mask.

5. The method for forming a semiconductor device with a vertical gate as claimed in claim 4 , wherein the mask layer comprises titanium nitride.

6. The method for forming a semiconductor device with a vertical gate as claimed in claim 1 , wherein the adhesion layer has a thickness of 5 nm-20 nm.

7. The method for forming a semiconductor device with a vertical gate as claimed in claim 1 , wherein the adhesion layer is formed by sequential flow deposition (SFD).

8. The method for forming a semiconductor device with a vertical gate as claimed in claim 7 , wherein the sequential flow deposition comprises:

performing a cycle of deposition, which comprises:

introducing titanium tetrachloride (TiCl4) and ammonia (NH3) into a deposition chamber to perform a deposition step;

performing a first purge step;

introducing ammonia (NH3) into the deposition chamber to perform a first nitrification step;

performing a second purge step;

introducing a silicon-containing gas into the deposition chamber;

performing a third purge step;

introducing ammonia (NH3) into the deposition chamber to perform a second nitrification step, and

repeating the cycle of deposition 5-20 times.

9. The method for forming a semiconductor device with a vertical gate as claimed in claim 8 , wherein the silicon-containing gas comprises silane (SiH4) or disilane (Si2H6).

10. A semiconductor device with a vertical gate, comprising:

a substrate, comprising a recess therein;

a gate dielectric layer overlying the substrate and on a sidewall and a bottom of the recess;

a polysilicon layer overlying the gate dielectric layer, wherein the polysilicon layer comprises source/drain regions therein and the substrate is separated from the source/drain regions by the gate dielectric layer;

an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer; and

a gate layer in the recess and on the adhesion layer.

11. The semiconductor device with a vertical gate as claimed in claim 10 , wherein there is substantially no void between the gate layer and the gate dielectric layer.

12. The semiconductor device with a vertical gate as claimed in claim 10 , wherein the metal of the metal silicide nitride layer is titanium, tantalum or tungsten.

13. The semiconductor device with a vertical gate as claimed in claim 10 , wherein the gate layer comprises titanium nitride (TiN).

14. The semiconductor device with a vertical gate as claimed in claim 10 , wherein the adhesion layer has a thickness of 5 nm-20 nm.