Memory interface supporting both ECC and per-byte data masking
A memory and a method of storing data in a memory are provided. The memory comprises a memory block comprising data bits and additional bits. The memory includes logic which, when receiving a first command, writes data into the data bits of the memory block, wherein the data is masked according to a first input. The logic, in response to a second command, writes data into the data bits of the memory block and writes a second input into the additional bits of the memory block.
1. A memory comprising:
a memory block comprising data bits and additional bits; and
logic configured to:
receive a first and a second input;
mask data in response to the first input;
respond to a first command, wherein the response includes:
writing the masked data into the data bits of the memory block, and writing “don't care” values into the additional bits of the memory block; and
respond to a second command, wherein the response includes:
writing the data into the data bits of the memory block, and
writing the second input into the additional bits of the memory block.
2. The memory of claim 1 , wherein the memory further comprises a bus channel input configured to receive the first input and the second input.
3. The memory of claim 1 , wherein the memory further comprises a first bus channel input configured to receive the first input and a second bus channel input configured to receive the second input.
4. The memory of claim 1 , wherein the response to the first command further includes writing a per-byte parity bit into the additional bits.
5. The memory of claim 1 , wherein the data is masked according to a per-byte bit mask.
6. The memory of claim 1 , wherein the logic is further configured to respond to a third command, wherein the response includes:
outputting the data from the data bits and the additional bits.
7. The memory of claim 1 , wherein the memory further comprises a mode bit, and wherein the first command comprises a write command when the mode bit is set to a first value, and wherein the second command comprises the write command when the mode bit set to a second value.
8. A method comprising:
receiving a first and a second input;
masking data in response to the first input;
transmitting, to a memory, a first command, wherein the memory includes a memory block comprising data bits and additional bits;
responding to the first command, wherein the response includes:
writing the masked data into data bits of the memory block, and writing “don't care” values into the additional bits of the memory block; and
transmitting, to the memory, a second command; and responding to the second command, wherein the response includes:
writing the data into the data bits of the memory block and
writing the second input to the memory into additional bits of the memory block.
9. The method of claim 8 , wherein transmitting the first command comprises transmitting the first command on a bus and wherein transmitting the second command comprises transmitting the second command on the bus.
10. The method of claim 8 , wherein transmitting the first command comprises transmitting the first command on a first bus and wherein transmitting the second command comprises transmitting the second command on a second bus.
11. The method of claim 8 , wherein the response to the first command further includes writing a per-byte parity bit into the additional bits.
12. The method of claim 8 , wherein the data is masked according to a per-byte bit mask.
13. The method of claim 8 , wherein the method further comprises:
transmitting to the memory, a third command;
and responding to the third command, wherein the response includes outputting the data from the data bits and the additional bits is output.
14. The method of claim 8 , wherein the first command is issued responsive to an address of the data bits being in a first set of addresses, and wherein the second command is issued responsive to the address being in a second set of addresses.
15. The method of claim 8 , wherein the first command is issued responsive to a determination that the memory does not support additional bits.
16. The method of claim 8 , wherein the second command is issued responsive to a determination that the memory supports additional bits.
17. A method comprising:
receiving a first and a second input;
masking data in response to the first input;
receiving, by a memory, a first command, wherein the memory includes a memory block comprising data bits and additional bits;
responding to the first command, wherein the response includes:
writing the masked data into data bits of the memory block, and writing “don't care” values into the additional bits of the memory block;
receiving, by the memory, a second command;
and responding to the second command, wherein the response includes:
writing the data into the data bits of the memory block and
writing a second input to the memory into additional bits of the memory block.
18. The method of claim 17 , wherein receiving the first command comprises receiving the first command on a bus and wherein receiving the second command comprises receiving the second command on the bus.
19. The method of claim 17 , wherein receiving the first command comprises receiving the first command on a first bus and wherein receiving the second command comprises receiving the second command on a second bus.
20. The method of claim 17 , wherein the first command causes the memory to write a per-byte parity bit into the additional bits.
21. The method of claim 17 , wherein the data is masked according to a per-byte bit mask.
22. The method of claim 17 , wherein the method further comprises:
receiving a third command; and
responding to the third command, wherein the response includes outputting the data from the data bits and the additional bits.