Reduced pin full feature load switch
A four pin integrated circuit MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) load switch is disclosed that provides full features including adjustable ramp time/rate, adjustable discharge time/rate, temperature control, over-current control, and short circuit protection. In some embodiments, the adjustable ramp is based on the voltage or current input into the integrated circuit.
1. An integrated circuit, comprising:
a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) configured as a switch; and
circuitry for providing an adjustable ramp rate for MOSFET turn-on, wherein a value of the ramp rate depends on a voltage level on an input pin of the integrated circuit;
wherein the integrated circuit comprises only four pins including the input pin, a drain pin, a source pin, and a ground pin.
2. The integrated circuit of claim 1 , wherein the switch comprises a load switch.
3. The integrated circuit of claim 1 , wherein the switch comprises a high-side load switch.
4. The integrated circuit of claim 1 , wherein the ramp rate is linear and closed loop.
5. The integrated circuit of claim 1 , wherein the value of the ramp rate is inversely proportional to the voltage level on the input pin.
6. The integrated circuit of claim 1 , wherein the voltage level on the input pin is set by an external voltage divider.
7. The integrated circuit of claim 1 , wherein the voltage level on the input pin comprises a discrete voltage level.
8. The integrated circuit of claim 1 , wherein the circuitry for providing an adjustable ramp rate is configured to translate voltage input into the integrated circuit into a linear, closed loop ramp.
9. The integrated circuit of claim 1 , wherein an adjustable discharge is provided via an external discharge resistor placed in series with the ground pin of the integrated circuit.
10. The integrated circuit of claim 1 , wherein the circuitry for providing an adjustable ramp rate comprises a voltage controlled current source that feeds a capacitor.
11. The integrated circuit of claim 1 , further comprising circuitry for over-temperature protection.
12. The integrated circuit of claim 1 , further comprising circuitry for over-current protection.
13. The integrated circuit of claim 1 , further comprising circuitry for short circuit protection.
14. A method, comprising:
configuring a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) as a switch; and
configuring circuitry for providing an adjustable ramp rate for MOSFET turn-on;
wherein the MOSFET and the circuitry form a four pin integrated circuit comprising an input pin, a drain pin, a source pin, and a ground pin and wherein a value of the ramp rate depends on a voltage level on the input pin of the integrated circuit.
15. The method of claim 14 , wherein the ramp rate is linear and closed loop.
16. The method of claim 14 , wherein the value of the ramp rate is inversely proportional to the voltage level on the input pin.
17. The method of claim 14 , wherein the circuitry for providing an adjustable ramp rate comprises a voltage controlled current source that feeds a capacitor.
18. The method of claim 14 , further comprising configuring circuitry for over-temperature protection.
19. The method of claim 14 , further comprising configuring circuitry for over-current protection.
20. The method of claim 14 , further comprising configuring circuitry for short circuit protection.
21. The integrated circuit of claim 1 , wherein the voltage level on the input pin is driven from a DAC (digital-to-analog converter).
22. The integrated circuit of claim 1 , wherein the voltage level on the input pin is driven from a PWM (pulse width modulator).
23. The method of claim 14 , wherein the switch comprises a load switch.
24. The method of claim 14 , wherein the switch comprises a high-side load switch.
25. The method of claim 14 , wherein the voltage level on the input pin is set by an external voltage divider.
26. The method of claim 14 , wherein the voltage level on the input pin comprises a discrete voltage level.
27. The method of claim 14 , wherein the circuitry for providing an adjustable ramp rate is configured to translate voltage input into the integrated circuit into a linear, closed loop ramp.
28. The method of claim 14 , further comprising placing an external discharge resistor in series with the ground pin of the integrated circuit to provide an adjustable discharge.
29. The method of claim 14 , wherein the voltage level on the input pin is driven from a DAC (digital-to-analog converter).
30. The method of claim 14 , wherein the voltage level on the input pin is driven from a PWM (pulse width modulator).