IP Library › Granted Patent US 9,070,379
Granted Patent B2
US 9,070,379 · App. 14/086,916 · Granted Jun 30, 2015

Data migration for data storage device

Inventor: Robert L. Horn (Yorba Linda, CA)
Assignee: Western Digital Technologies, Inc.
G11B5/09G06F3/0617G06F3/0647G06F3/0685
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Quick Facts
Patent No.
US 9,070,379
App. No.
14/086,916
Granted
Jun 30, 2015
Kind
B2
Abstract

Migration of data in a data storage device (DSD). A spindle motor of the DSD is controlled to rotate a disk of the DSD to perform at least one operation on the disk and an operational activity level is determined for performing the at least one operation. It is determined whether the operational activity level is greater than a target level, and if it is determined that the operational activity level is not greater than the target level, data is transferred between a solid state memory of the DSD and the disk while the disk rotates.

Claims (57)

1. A data storage device (DSD), comprising:

a disk for storing data;

a spindle motor for rotating the disk;

a solid state memory for storing data; and

a controller configured to:

control the spindle motor to rotate the disk to perform at least one operation on the disk;

determine a number of commands queued for performing the at least one operation;

determine whether the number of commands queued is greater than a target level of commands; and

if it is determined that the number of commands queued is not greater than the target level, transfer data between the solid state memory and the disk to increase the number of commands queued to reach the target level while the disk rotates.

2. The DSD of claim 1 , wherein the controller is further configured to set the target level based on a performance limit for performing operations on the disk.

3. The DSD of claim 1 , wherein the data transferred between the solid state memory and the disk includes dirty data transferred from the solid state memory to the disk, the dirty data including data that is most recently written for a logical address and that can be used to update the disk by writing the dirty data to the disk for the logical address.

4. The DSD of claim 1 , wherein the data transferred between the solid state memory and the disk includes at least one of frequently accessed data and high priority data transferred from the disk to the solid state memory.

5. The DSD of claim 1 , wherein the controller is further configured to set an amount of data to be transferred between the solid state memory and the disk to reach the target level while transferring the data.

6. The DSD of claim 1 , wherein the controller is further configured to adjust the target level based on at least one of an amount of data to be transferred between the disk and the solid state memory, an available capacity of the solid state memory, an amount of dirty data stored in the solid state memory, and an age of dirty data stored in the solid state memory, wherein the dirty data includes data that is most recently written for a logical address and can be used to update the disk by writing the dirty data to the disk for the logical address.

7. The DSD of claim 1 , wherein the controller is further configured to select data to transfer between the solid state memory and the disk based on an addressing of data involved in performing the at least one operation.

8. The DSD of claim 1 , further comprising a head for reading and writing data on the disk, wherein the controller is further configured to select data to transfer between the solid state memory and the disk so as to reduce motion of the head in relation to the disk.

9. The DSD of claim 1 , wherein the at least one operation includes a data maintenance operation on the disk, and the controller is further configured to:

determine a range of logical addresses for performing the data maintenance operation on the disk; and

select data to transfer between the solid state memory and the disk so that the selected data is addressed with logical addresses within the range of logical addresses.

10. The DSD of claim 1 , wherein the controller is further configured to maintain a timer for entering a low power state of the DSD, and wherein the transfer of data between the solid state memory and the disk does not delay the timer for entering the low power state such that if the timer expires while data is being transferred between the solid state memory and the disk, the DSD enters the low power state upon the completion of the transferring of data between the solid state memory and the disk.

11. The DSD of claim 1 , wherein the controller is further configured to:

maintain a first queue of pending operations for performance by the DSD;

maintain a second queue of pending operations for performance by the DSD; and

sequence performance of the pending operations in the first queue with the pending operations in the second queue based on a predetermined quality of service for performing the pending operations in at least one of the first queue and the second queue;

wherein the pending operations in the first queue include pending data transfer operations between the solid state memory and the disk, pending maintenance operations for the disk, or pending host command operations for host commands received from a host in communication with the DSD.

12. A method for migrating data in a data storage device (DSD), the method comprising:

controlling a spindle motor of the DSD to rotate a disk of the DSD to perform at least one operation on the disk;

determining a number of commands queued for performing the at least one operation;

determining whether the number of commands queued is greater than a target level of commands; and

if it is determined that the number of commands queued is not greater than the target level, transferring data between a solid state memory of the DSD and the disk to increase the number of commands queued to reach the target level while the disk rotates.

13. The method of claim 12 , further comprising setting the target level based on a performance limit for performing operations on the disk.

14. The method of claim 12 , wherein the data transferred between the solid state memory and the disk includes dirty data transferred from the solid state memory to the disk, the dirty data including data that is most recently written for a logical address and that can be used to update the disk by writing the dirty data to the disk for the logical address.

15. The method of claim 12 , wherein the data transferred between the solid state memory and the disk includes at least one of frequently accessed data and high priority data transferred from the disk to the solid state memory.

16. The method of claim 12 , further comprising setting an amount of data to be transferred between the solid state memory and the disk to reach the target level while transferring the data.

17. The method of claim 12 , further comprising adjusting the target level based on at least one of an amount of data to be transferred between the disk and the solid state memory, an available capacity of the solid state memory, an amount of dirty data stored in the solid state memory, and an age of dirty data stored in the solid state memory, wherein the dirty data includes data that is most recently written for a logical address that can be used to update the disk by writing the dirty data to the disk for the logical address.

18. The method of claim 12 , further comprising selecting data to transfer between the solid state memory and the disk based on an addressing of data involved in performing the at least one operation.

19. The method of claim 12 , further comprising selecting data to transfer between the solid state memory and the disk so as to reduce motion of a head in relation to the disk, wherein the head is configured to read and write data on the disk.

20. The method of claim 12 , wherein the at least one operation includes a data maintenance operation on the disk, and wherein the method further comprises:

determining a range of logical addresses for performing the data maintenance operation on the disk; and

selecting data to transfer between the solid state memory and the disk so that the selected data is addressed with logical addresses within the range of logical addresses.

21. The method of claim 12 , further comprising maintaining a timer for entering a low power state of the DSD, wherein the transferring of data between the solid state memory and the disk does not delay the timer for entering the low power state such that if the timer expires while data is being transferred between the solid state memory and the disk, the DSD enters the low power state upon the completion of the transferring of data between the solid state memory and the disk.

22. The method of claim 12 , wherein the method further comprises:

maintaining a first queue of pending operations for performance by the DSD;

maintaining a second queue of pending operations for performance by the DSD; and

sequencing performance of the pending operations in the first queue with pending operations in the second queue based on a predetermined quality of service for performing the pending operations in at least one of the first queue and the second queue;

wherein the pending operations in the first queue include pending data transfer operations between the solid state memory and the disk, pending maintenance operations for the disk, or pending host command operations received for host commands received from a host in communication with the DSD.

23. A data storage device (DSD), comprising:

a disk for storing data;

a spindle motor for rotating the disk;

a solid state memory for storing data; and

a controller configured to:

control the spindle motor to rotate the disk to perform at least one operation on the disk;

determine a number of operations performed during a period of time in performing the at least one operation;

determine whether the number of operations performed during the period of time is greater than a target level; and

if it is determined that the number of operations performed during the period of time is not greater than the target level, transfer data between the solid state memory and the disk to increase a number of operations performed on the disk to reach the target level while the disk rotates.

24. The DSD of claim 23 , wherein the controller is further configured to set the target level based on a performance limit for performing operations on the disk.

25. The DSD of claim 23 , wherein the data transferred between the solid state memory and the disk includes dirty data transferred from the solid state memory to the disk, the dirty data including data that is most recently written for a logical address and that can be used to update the disk by writing the dirty data to the disk for the logical address.

Assignments (9)
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 038744 FRAME 0481 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0556 →
RELEASE OF SECURITY INTEREST Recorded Mar 5, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045501/0714 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038722/0229 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038744/0281 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038744/0481 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2014
From: HORN, ROBERT L.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 033469/0725 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2013
From: HORN, ROBERT L.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 031654/0423 →
Continuity (2)
Provisional Application 61871270 · Aug 28, 2013
Related Publication 20150062743A1 · Mar 5, 2015