Semiconductor device
A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1, a first electrode pad 21 laminated on the semiconductor chip 1, an intermediate layer 4 having a rectangular shape defined by first edges 49 a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1 . The first edges 49 a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21 . The first bump 51 is arranged at one end in the direction x and one end in the direction y.
1. A semiconductor device comprising:
a semiconductor chip comprising a semiconductor substrate, a wiring layer formed directly on the semiconductor substrate, and an insulating layer covering the wiring layer;
a first electrode pad laminated on the insulating layer of the semiconductor chip;
a second electrode pad laminated on the insulating layer of the semiconductor chip;
an intermediate layer having a rectangular shape defined by a first edge and a second edge; and
a plurality of bumps arranged to sandwich the intermediate layer by cooperating with the semiconductor chip;
wherein the first edge extends in a first direction crossing a thickness direction of the semiconductor chip, the second edge extends in a second direction crossing both of the thickness direction and the first direction, the plurality of bumps include a first bump electrically connected to the first electrode pad, the plurality of bumps include a second bump electrically connected to the first electrode pad via the second electrode pad, and the first bump is arranged at one end in the first direction and one end in the second direction, and
wherein both the first electrode pad and the second electrode pad are electronically connected to the wiring layer of the semiconductor chip, and
wherein the first bump and the second bump are placed along and adjacent to the first edge of the intermediate layer.
2. The semiconductor device according to claim 1 , further comprising a coating film that exposes the first electrode pad and the second electrode pad,
wherein the intermediate layer includes a stress buffer layer laminated on the coating film, a first re-distribution layer laminated on the stress buffer layer and a second re-distribution layer laminated on the stress buffer layer, the first re-distribution layer includes a portion that overlaps the first bump as viewed in the thickness direction, the second re-distribution layer includes a portion that overlaps the second bump as viewed in the thickness direction, and the first re-distribution layer and the second re-distribution layer are spaced apart from each other.
3. The semiconductor device according to claim 1 , further comprising a coating film that exposes the first electrode pad and the second electrode pad,
wherein the intermediate layer includes a stress buffer layer laminated on the coating film and a re-distribution layer laminated on the stress buffer layer, and the re-distribution layer electrically connects the first bump and the second bump to each other.
4. The semiconductor device according to claim 1 , further comprising a coating film that exposes the first electrode pad,
wherein the intermediate layer includes a stress buffer layer laminated on the coating film and a re-distribution layer laminated on the stress buffer layer, and the re-distribution layer electrically connects the first bump and the second bump to each other.
5. The semiconductor device according to claim 1 , wherein the intermediate layer includes a first post extending in the thickness direction of the semiconductor chip and a second post extending in the thickness direction of the semiconductor chip, the first post is in contact with the first bump, and the second post is in contact with the second bump.
6. The semiconductor device according to claim 5 , wherein a bonding area between the first post and the first bump is larger than a bonding area between the second post and the second bump.
7. The semiconductor device according to claim 5 , wherein a cross section of the first post within a plane spreading in the first direction and the second direction is larger than a cross section of the second post within a plane spreading in the first direction and the second direction.
8. The semiconductor device according to claim 5 , wherein the first post is in a form of a round column having a diameter of a first dimension and elongated in the thickness direction, and the second post is in a form of a round column having a diameter of a second dimension smaller than the first dimension and elongated in the thickness direction.
9. The semiconductor device according to claim 8 , wherein the first dimension is 1.1 to 1.5 times the second dimension.
10. The semiconductor device according to claim 1 , wherein the intermediate layer includes a substrate with an obverse surface and a reverse surface, an obverse surface wiring layer formed on the obverse surface, and a reverse surface wiring layer formed on the reverse surface, the reverse surface faces away from the obverse surface, the semiconductor chip is mounted on the obverse surface, the reverse surface wiring layer is electrically connected to the obverse surface wiring layer, and the reverse surface wiring layer is in contact with both of the first bump and the second bump.
11. The semiconductor device according to claim 1 , wherein the first bump and the second bump are equal in volume.
12. The semiconductor device according to claim 1 , wherein the plurality of bumps comprise at least twenty-five bumps.
13. The semiconductor device according to claim 1 , wherein the first bump has a circular shape having a diameter of a first length as viewed in the thickness direction, and the second bump has a circular shape having a diameter of a second length smaller than the first length as viewed in the thickness direction.
14. The semiconductor device according to claim 13 , wherein the first length is 1.1 to 1.5 times the second length.
15. The semiconductor device according to claim 1 , wherein the second bump is closest to the first bump among the plurality of bumps.
16. The semiconductor device according to claim 1 , wherein both of the first bump and the second bump are functional pins.
17. The semiconductor device according to claim 1 , wherein the plurality of bumps comprise bumps arranged as the first bump at four corners.
18. The semiconductor device according to claim 4 , wherein the intermediate layer further includes a resin layer laminated on the stress buffer layer or the re-distribution layer.
19. The semiconductor device according to claim 18 , wherein the resin layer covers a side surface of the stress buffer layer.
20. The semiconductor device according to claim 19 , wherein the resin layer further covers a side surface of the coating film.
21. The semiconductor device according to claim 18 , further comprising a resin coat covering a reverse surface of the semiconductor chip.
22. The semiconductor device according to claim 18 , wherein the re-distribution layer comprises a base layer and a metal layer.
23. The semiconductor device according to claim 22 , wherein the base layer is made of one of titanium, nickel and titanium tungsten, and the metal layer is made of copper.