Scanning signal line drive circuit, display device having the same, and drive method for scanning signal line
The present invention is directed to suppress dullness of a scanning signal in a scanning signal line drive circuit. A bistable circuit is provided with an input terminal ( 43 ) for receiving a first clock signal (CK), an input terminal ( 48 ) for receiving a control signal (CT), an input terminal ( 49 ) for receiving a level down signal (LD), an output terminal ( 51 ), a thin film transistor (T 2 ), and a thin film transistor (TA). The thin film transistor (T 2 ) has a gate terminal connected to a first node (N 1 ), a drain terminal connected to the input terminal ( 43 ), and a source terminal connected to the output terminal ( 51 ). The thin film transistor (TA) has a gate terminal connected to the input terminal ( 48 ), a drain terminal connected to the first node (N 1 ), and a source terminal connected to the input terminal ( 49 ). The potential of the control signal (CT) becomes the high level in a control period as a period except for the first one horizontal scanning period in a vertical blanking period. The level down signal (LD) is a potential lower than DC power supply potential (Vss).
1. A scanning signal line drive circuit for periodically driving a plurality of scanning signal lines, the scanning signal line drive circuit comprising:
a shift register including a plurality of bistable circuits which are cascade-connected to one another and sequentially making output signals of the plurality of bistable circuits active based on clock signals which are supplied from the outside and periodically repeats an on level and an off level, wherein
each of the bistable circuits comprises:
a drive unit having a first node and changing a potential of the first node based on a set signal; and
an output unit connected to the first node and, when the potential of the first node is at the on level, outputting one of the output signals which is active based on the clock signals,
the set signal in the bistable circuit in a front stage is a start pulse signal which becomes an on level at a scanning start timing,
the set signal in the bistable circuit in a stage other than the front stage is an output signal of the bistable circuit of a preceding stage,
the output unit has an output control switching element having a control terminal connected to the first node, a conduction terminal to which one of the clock signals is supplied, and another conduction terminal connected to an output node for outputting one of the output signals, and
the drive unit has a first node level down switching element having a control terminal to which a control signal whose potential becomes the on level in a control period as a predetermined period in a vertical blanking period in which all of the output signals of the plurality of bistable circuits are inactive is supplied, a conduction terminal connected to the first node, and another conduction terminal to which a level down signal which becomes a level down potential as a potential lower than the off level at least in the control period is supplied.
2. The scanning signal line drive circuit according to claim 1 , wherein
the clock signals include a first clock signal and a second clock signal whose phases are deviated from each other only by one horizontal scanning period,
the first clock signal is supplied to the conduction terminal of the output control switching element, and
the drive unit further comprises:
a second node;
a second-node-on-time first node turn off switching element having a control terminal connected to the second node, a conduction terminal connected to the first node, and another conduction terminal to which a potential at the off level is supplied;
a second node variation switching element for changing a potential of the second node based on the second clock signal; and
a first-clock-signal-on-time second node turn off switching element having a control terminal to which the first clock signal is supplied, a conduction terminal connected to the second node, and another conduction terminal to which a potential at the off level is supplied.
3. The scanning signal line drive circuit according to claim 2 , wherein supply of the first clock signal and the second clock signal to the plurality of bistable circuits is stopped in the control period.
4. The scanning signal line drive circuit according to claim 3 , wherein the drive unit further comprises a control period second node turn off switching element having a control terminal to which the control signal is supplied, a conduction terminal connected to the second node, and another conduction terminal to which a potential at the off level is supplied.
5. The scanning signal line drive circuit according to claim 2 , wherein the drive unit further comprises a first clock level down switching element having a control terminal to which the control signal is supplied, a conduction terminal connected to the control terminal of the first-clock-signal-on-time second node turn off switching element, and another conduction terminal to which the level down signal is supplied.
6. The scanning signal line drive circuit according to claim 5 , wherein in the control period, supply of the first clock signal to the plurality of bistable circuits is stopped, and a terminal of each bistable circuit for receiving the first clock signal enters a high impedance state.
7. The scanning signal line drive circuit according to claim 2 , wherein the drive unit further comprises a second clock level down switching element having a control terminal to which the control signal is supplied, a conduction terminal connected to the control terminal and the conduction terminal of the second node variation switching element, and another conduction terminal to which the level down signal is supplied.
8. The scanning signal line drive circuit according to claim 7 , wherein in the control period, supply of the second clock signal to the plurality of bistable circuits is stopped, and a terminal of each bistable circuit for receiving the second clock signal enters a high impedance state.
9. The scanning signal line drive circuit according to claim 1 , wherein the drive unit further comprises a first node turn on switching element which changes the potential of the first node toward the on level based on the set signal.
10. The scanning signal line drive circuit according to claim 1 , wherein the drive unit further comprises a set-time second node turn off switching element having a control terminal connected to the first node, a conduction terminal connected to the second node, and another conduction terminal to which a potential at the off level is supplied.
11. The scanning signal line drive circuit according to claim 1 , wherein the output unit further comprises a capacitive element having one end connected to the control terminal of the output control switching element and another end connected to the output node.
12. The scanning signal line drive circuit according to claim 1 , wherein the drive unit further comprises a reset-time first node turn off switching element having a control terminal to which a reset signal as an output signal of the bistable circuit at a post stage of the bistable circuit having the drive unit is supplied, a conduction terminal connected to the first node, and another conduction terminal to which a potential at the off level is supplied, and
the output unit further comprises an output node turn off switching element having a control terminal to which the reset signal is supplied, a conduction terminal connected to the output node, and another conduction terminal to which a potential at the off level is supplied.
13. A display device comprising:
a display unit in which a plurality of scanning signal lines are arranged;
a scanning signal line drive circuit for periodically driving the plurality of scanning signal lines; and
a display control circuit supplying clock signals which periodically repeat an on level and an off level, to the scanning signal line drive circuit, wherein
the scanning signal line drive circuit includes a shift register having a plurality of bistable circuits which are cascade-connected to one another and sequentially making output signals of the plurality of bistable circuits active based on the clock signals,
each of the bistable circuits comprises:
a drive unit having a first node and changing a potential of the first node based on a set signal; and
an output unit connected to the first node and, when the potential of the first node is at the on level, outputting one of the output signals which is active based on the clock signals,
the set signal in the bistable circuit in a front stage is a start pulse signal which becomes an on level at a start timing of each of vertical scanning periods,
the set signal in the bistable circuit in a stage other than the front stage is an output signal of the bistable circuit of a preceding stage,
the output unit has an output control switching element having a control terminal connected to the first node, a conduction terminal to which one of the clock signals is supplied, and another conduction terminal connected to an output node for outputting one of the output signals, and
the drive unit has a first node level down switching element having a control terminal to which a control signal whose potential becomes the on level in a control period as a predetermined period in a vertical blanking period in which all of the output signals of the plurality of bistable circuits are inactive is supplied, a conduction terminal connected to the first node, and another conduction terminal to which a level down signal which becomes a level down potential as a potential lower than the off level at least in the control period is supplied.
14. The display device according to claim 13 , wherein the display unit and the scanning signal line drive circuit are integrally formed.
15. A drive method for a plurality of scanning signal lines by a scanning signal line drive circuit comprising a shift register including a plurality of bistable circuits which are cascade-connected to one another and sequentially making output signals of the plurality of bistable circuits active based on clock signals which are supplied from the outside and periodically repeat an on level and an off level, the drive method comprising the steps of:
changing a potential of a first node of each bistable circuit based on a set signal received by each bistable circuit; and
outputting one of the output signals which is active based on one of the clock signals when the potential of the first node is at the on level, wherein
each bistable circuit has an output control switching element having a control terminal connected to the first node, a conduction terminal to which one of the clock signals is supplied, and another conduction terminal connected to an output node for outputting one of the output signals,
the set signal received by the bistable circuit in a front stage is a start pulse signal which becomes an on level at a scanning start timing,
the set signal received by the bistable circuit in a stage other than the front stage is an output signal of the bistable circuit of a preceding stage, and
the step of changing the potential of the first node includes a step of setting the potential of the first node to a level down potential as a potential which is lower than the off level at least in a control period as a predetermined period in a vertical blanking period in which all of the output signals of the plurality of bistable circuits are inactive.