Selective local metal cap layer formation for improved electromigration behavior
A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.
1. A method of forming a wiring structure for an integrated circuit device, the method comprising:
forming one or more copper lines within an interlevel dielectric (ILD) layer;
masking selected regions of the one or more copper lines such that first portions of the one or more copper lines are covered and second portions of the copper lines are not covered so as to define exposed regions, the masking selected regions comprising forming a sacrificial hardmask layer over the ILD layer and one or more copper lines, and patterning and removing portions of the sacrificial hardmask layer;
selectively plating metal cap regions over only the exposed regions of the one or more copper lines such that the metal cap regions are not initially plated over the covered portions of the one or more copper lines;
following the plating of the metal cap regions over the exposed regions of the one or more copper lines, removing remaining portions of the sacrificial hardmask layer; and
forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines, and the ILD layer.
2. The method of claim 1 , further comprising plating the metal cap regions at periodic intervals such that a spacing between adjacent metal cap regions corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the one or more copper lines, so as to suppress mass transport of electrons.
3. The method of claim 2 , wherein the metal cap regions comprise one or more of: tantalum, (Ta), tantalum nitride (TaN), cobalt (Co), cobalt tungsten phosphide (CoWP), and ruthenium (Ru).
4. The method of claim 1 , wherein patterning and removing portions of the sacrificial hardmask layer further comprises etching into a top surface of the copper line such that at least a portion of the metal cap regions is disposed below the top surface of the copper line.
5. The method of claim 1 , wherein the sacrificial hardmask layer comprises:
a hydrogen doped silicon nitride layer formed on the ILD layer and one or more copper lines;
a titanium nitride layer formed on the hydrogen doped silicon nitride layer;
a low temperature oxide (LTO) layer formed on the titanium nitride layer; and
an organic planarizing layer (OPL) formed over the LTO layer.
6. The method of claim 5 , wherein patterning and removing portions of the sacrificial hardmask layer further comprises:
defining a pattern in the OPL and the LTO layer;
transferring the pattern through the titanium nitride layer and partially into the hydrogen doped silicon nitride layer;
removing the OPL and the LTO layer by ashing;
removing the titanium nitride layer by etching;
transferring the pattern completely through the hydrogen doped silicon nitride layer; and
following the plating of the metal cap regions, removing remaining portions of the hydrogen doped silicon nitride layer.