Compliant printed circuit semiconductor package

1. A method of making a package for a semiconductor device having electrical terminals, the method comprising the step of:

locating at least one semiconductor device on a substrate;

printing a first dielectric layer on at least a portion of the semiconductor device comprising first recesses aligned with a plurality of the electrical terminals;

depositing a conductive material in the first recesses forming contact members on the semiconductor device;

printing a second dielectric layer on at least a portion of the first dielectric layer comprising second recesses aligned with a plurality of the first recesses;

depositing a conductive material in at least a portion of the second recesses comprising a circuit geometry, the circuit geometry comprising a plurality of exposed terminals; and

depositing a compliant material in recesses in one or more of the first and second dielectric layers adjacent to a plurality of the exposed terminals to permit the exposed terminals to move within the dielectric layers relative to the substrate.

2. The method of claim 1 comprising the step of depositing a conductive plating layer on one or more of the contact members, the exposed terminals, and the circuit geometry.

3. The method of claim 1 comprising locating the compliant material between the exposed terminals and the substrate.

4. The method of claim 1 comprising:

printing at least one electrical device on one of a dielectric layer or the substrate; and

electrically coupled the electrical device to at least a portion of the circuit geometry.

5. The method of claim 1 depositing conductive materials so the exposed terminals extend above the package.

6. The method of claim 1 comprising depositing a conductive material in the recesses for form a plurality of vias electrically coupling adjacent layers of the package.

7. The method of claim 1 comprising the steps of:

forming at least one external dielectric layer extending beyond the package; and

depositing a conductive material on the external dielectric layer forming external routing electrically coupled to a portion of the circuit geometry.

8. The method of claim 1 comprising the steps of:

locating a plurality of semiconductor devices on the substrate; and

depositing the conductive material so the circuit geometry to include at least one inter-die circuit path or intra-die circuit paths.

9. The method of claim 1 comprising the steps of:

stacking at least two semiconductor devices vertically on the substrate; and

electrically coupling at least two of the stacked semiconductor devices with a plurality of through silicon vias.

10. The method of claim 1 comprising the steps of:

locating a plurality of semiconductor devices on the substrate; and

electrically coupling the plurality of semiconductor devices with the circuit geometry.

11. The method of claim 1 comprising the step of arranging a conductive material, a non-conductive material, and a semi-conductive material on a single layer of the package.

12. The method of claim 1 comprising locating the exposed terminals offset from the electric terminals on the semiconductor device.

13. The method of claim 1 comprising encapsulating the semiconductor device to the substrate so that the semiconductor device is electrically accessible via the exposed terminals.

14. The method of claim 1 comprising depositing the compliant material so the exposed terminals can move relative to the substrate.

15. The method of claim 1 comprising depositing the resilient material so the exposed terminal can move in at least three degrees of freedom relative to the substrate.

16. The method of claim 1 comprising the steps of:

locating pre-formed conductive trace materials in the second recesses; and

plating the second recesses.

17. The method of claim 1 comprising the steps of:

pressing a conductive foil into at least a portion of the second recesses;

shearing the conductive foil along edges of the second recesses;

removing excess conductive foil not located in the second recesses; and

plating the second recesses to form conductive traces.

18. A method of making an electrical assembly comprising the steps of:

forming the package of claim 1 ; and

electrically coupling the exposed terminals on the package with a plurality of contact pads on a circuit member.

19. The method of making an electrical assembly of claim 18 comprising selecting the circuit member from one of a dielectric layer, a printed circuit board, a flexible circuit, a bare die device, an integrated circuit device, organic or inorganic substrates, or a rigid circuit.

20. A method of making a package for a semiconductor device having electrical terminals, the method comprising the step of:

locating at least one semiconductor device on a substrate;

printing a first dielectric layer on at least a portion of the semiconductor device comprising first recesses aligned with a plurality of the electrical terminals;

depositing a conductive material in the first recesses forming contact members on the semiconductor device;

printing a second dielectric layer on at least a portion of the first dielectric layer comprising second recesses aligned with a plurality of the first recesses;

depositing a conductive material in at least a portion of the second recesses comprising a circuit geometry;

printing a third dielectric layer selectively printed on at least a portion of the second dielectric layer comprising third recesses aligned with a portion of the circuit geometry;

depositing a conductive material in the third recesses comprising a plurality of exposed terminals that are offset from, and electrically coupled to the electric terminals on the semiconductor device by the circuit geometry; and

depositing a compliant material in recesses in one or more of the first, second or third dielectric layers adjacent to a plurality of the exposed terminals to permit the exposed terminals to move within the dielectric layers relative to the substrate.