Successive approximation AD converter and noise generator
In a successive approximation AD converter, a noise generator outputs the output of a ΔΣ modulator as a noise signal. A selector circuit can output the noise signal, in place of a digital signal for generating a comparison-target voltage for the next bit, to a capacitor element of a capacitance DAC. During sampling of an analog input voltage, the noise signal is supplied to the capacitance DAC via the selector circuit, and thereafter normal successive approximation operation is executed.
1. A successive approximation AD converter configured to convert an analog input voltage to a digital value, comprising:
a capacitance DAC having a plurality of capacitor elements having weighted capacitance values, first terminals of the capacitor elements being connected to a common node and either a first or second reference voltage being selectively applied to second terminals thereof according to a first digital signal;
a comparator at least having an input connected to the common node of the capacitance DAC, configured to compare the analog input voltage with a comparison-target voltage generated by the capacitance DAC;
a successive approximation control section configured to set a second digital signal for generating the comparison-target voltage for the next bit from the comparison result of the comparator and output the second digital signal;
a noise generator having at least one ΔΣ modulator, configured to output an output of the ΔΣ modulator as a noise signal; and
a selector circuit provided for at least one of the plurality of capacitor elements, configured to select either the second digital signal or the noise signal for the capacitor element and output the selected signal as the first digital signal.
2. The successive approximation AD converter of claim 1 , wherein the selector circuit selects, as the first digital signal, the noise signal during sampling of the analog input voltage and the second digital signal after the sampling.
3. The successive approximation AD converter of claim 1 , further comprising:
a subtraction circuit configured to subtract a digital value corresponding to the noise signal from a multi-bit digital value converted from the output of the comparator.
4. The successive approximation AD converter of claim 1 , further comprising:
a digital filter circuit configured to remove an out-of-band signal from a multi-bit digital value converted from the output of the comparator.
5. The successive approximation AD converter of claim 1 , wherein
the noise generator has a plurality of ΔΣ modulators, and
the plurality of ΔΣ modulators are configured to output digital signals uncorrelated to each other.
6. A successive approximation AD converter configured to convert an analog input voltage to a digital value, comprising:
a capacitance DAC having a plurality of capacitor elements having weighted capacitance values, first terminals of the capacitor elements being connected to a common node and either a first or second reference voltage being selectively applied to second terminals thereof according to a first digital signal;
a comparator at least having an input connected to the common node of the capacitance DAC, configured to compare the analog input voltage with a comparison-target voltage generated by the capacitance DAC;
a successive approximation control section configured to set a second digital signal for generating the comparison-target voltage for the next bit from the comparison result of the comparator and output the second digital signal;
a capacitance DAC control circuit configured to select either a correction control signal or the second digital signal and output the selected signal to the capacitance DAC as the first digital signal; and
a ΔΣ modulator configured to receive a capacitance value control signal,
wherein the capacitance DAC has at least one variable capacitor element where a first terminal thereof is connected to the common node, either the first or second reference voltage is selectively applied to a second terminal thereof according to a bit as part of the second digital signal, and the capacitance value is controlled according to an output signal of the ΔΣ modulator.
7. The successive approximation AD converter of claim 6 , further comprising:
a digital filter circuit configured to remove an out-of-band signal from a multi-bit digital value converted from the output of the comparator.
8. The successive approximation AD converter of claim 6 , further comprising:
a correction control circuit configured to receive a multi-bit digital value converted from the output of the comparator and generate the correction control signal and the capacitance value control signal.
9. A successive approximation AD converter configured to convert an analog input voltage to a digital value, comprising:
a capacitance DAC having a plurality of capacitor elements having weighted capacitance values, first terminals of the capacitor elements being connected to a common node and either a first or second reference voltage being selectively applied to second terminals thereof according to a first digital signal, the capacitance DAC being divided into a higher-order DAC including capacitor elements corresponding to higher-order bits of the digital value and a lower-order DAC including capacitor elements corresponding to lower-order bits of the digital value, a coupling capacitor being inserted between the higher-order DAC and the lower-order DAC at the common node;
a comparator at least having an input connected to the common node of the capacitance DAC, configured to compare the analog input voltage with a comparison-target voltage generated by the capacitance DAC;
a successive approximation control section configured to set a second digital signal for generating the comparison-target voltage for the next bit from the comparison result of the comparator and output the second digital signal;
a higher-order DAC control circuit configured to select either a correction control signal or the second digital signal and output the selected signal to the higher-order DAC as the first digital signal; and
a ΔΣ modulator configured to receive a capacitance value control signal,
wherein the lower-order DAC has a variable capacitor element where a first terminal thereof is connected to the common node, a second terminal thereof is grounded, and the capacitance value is controlled according to an output signal of the ΔΣ modulator.
10. The successive approximation AD converter of claim 9 , further comprising:
a digital filter circuit configured to remove an out-of-band signal from a multi-bit digital value converted from the output of the comparator.
11. The successive approximation AD converter of claim 9 , further comprising:
a correction control circuit configured to receive a multi-bit digital value converted from the output of the comparator and generate the correction control signal and the capacitance value control signal.
12. A noise generator having a plurality of ΔΣ modulators, configured to supply output signals of the plurality of ΔΣ modulators as noise signals,
wherein the noise signals are signals obtained by individually adding differently-weighted values to the output signals of the ΔΣ modulators, and
the differently-weighted values are based on a binary ratio.
13. A noise generator having a plurality of ΔΣ modulators, configured to supply output signals of the plurality of ΔΣ modulators as noise signals,
wherein the noise signals are signals obtained by individually adding differently-weighted values to the output signals of the ΔΣ modulators, and
the plurality of ΔΣ modulators are different in order from each other.