ZrO-based high K dielectric stack for logic decoupling capacitor or embedded DRAM
A zirconium oxide based dielectric material is used in the formation of decoupling capacitors employed in microelectronic logic circuits. In some embodiments, the zirconium oxide based dielectric is doped. In some embodiments, the dopant includes at least one of aluminum, silicon, or yttrium. In some embodiments, the zirconium oxide based dielectric is formed as a nanolaminate of zirconium oxide and a dopant metal oxide.
1. A capacitor comprising:
a bottom electrode layer disposed above a surface of a substrate;
a dielectric stack disposed above the bottom electrode layer, wherein the dielectric stack comprises a nanolaminate of a high k material sub-layer and a high band gap material sub-layer, wherein the high k material sub-layer is formed by ALD deposition, wherein ozone having a concentration of 20 weight % is used as an oxidant during the ALD deposition,
wherein the high k material sub-layer is amorphous,
wherein the high band gap material sub-layer is amorphous; and a top electrode layer above disposed the dielectric stack.
2. The capacitor of claim 1 , wherein the bottom electrode layer comprises one or more of titanium nitride, titanium aluminum nitride, titanium silicon nitride, tantalum nitride, tantalum aluminum nitride, tantalum silicon nitride, or doped polysilicon.
3. The capacitor of claim 1 , wherein the bottom electrode layer comprises titanium nitride.
4. The capacitor of claim 1 , wherein the high k material comprises zirconium oxide.
5. The capacitor of claim 1 , wherein the high band gap material comprises at least one of silicon oxide, lanthanum oxide, or yttrium oxide.
6. The capacitor of claim 1 , wherein the top electrode layer comprises one or more of titanium nitride, titanium aluminum nitride, titanium silicon nitride, tantalum nitride, tantalum aluminum nitride, tantalum silicon nitride, or doped polysilicon.
7. The capacitor of claim 1 , wherein the top electrode layer comprises titanium nitride.
8. The capacitor of claim 1 , wherein the dielectric stack further comprises an additional high k material sub-layer, and wherein the high band gap material sub-layer is disposed between the high k material sub-layer and the additional high k material sub-layer.
9. The capacitor of claim 1 , wherein the high k material sub-layer further comprises a dopant selected from the group consisting of aluminum, silicon, or yttrium.
10. A method of forming a capacitor for use in a microelectronic logic circuit, the method comprising:
forming a bottom electrode layer above a surface of a substrate;
forming a dielectric stack above the bottom electrode layer, wherein forming the dielectric stack comprises forming a nanolaminate of a high k material sub-layer and a high band gap material sub-layer, wherein the high k material sub-layer is formed by ALD deposition, wherein ozone having a concentration of 20 weight % is used as an oxidant during the ALD deposition,
wherein the high k material sub-layer is amorphous, and
wherein the high band gap material sub-layer is amorphous; and forming a top electrode layer above the dielectric stack.
11. The method of claim 10 , wherein the bottom electrode layer comprises one or more of titanium nitride, titanium aluminum nitride, titanium silicon nitride, tantalum nitride, tantalum aluminum nitride, tantalum silicon nitride, or doped polysilicon.
12. The method of claim 10 , wherein the bottom electrode layer comprises titanium nitride.
13. The method of claim 10 , wherein the high k material comprises zirconium oxide.
14. The method of claim 10 , wherein the high band gap material comprises at least one of silicon oxide, lanthanum oxide, or yttrium oxide.
15. The method of claim 10 , wherein the top electrode layer comprises one or more of titanium nitride, titanium aluminum nitride, titanium silicon nitride, tantalum nitride, tantalum aluminum nitride, tantalum silicon nitride, or doped polysilicon.
16. The method of claim 10 , wherein the top electrode layer comprises titanium nitride.