Three-dimensional integrated circuit having stabilization structure for power supply voltage, and method for manufacturing same
The three-dimensional integrated circuit has a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, wherein each of the first semiconductor chip and the second semiconductor chip is provided with a power supply wiring layer which has a wiring pattern structure for stably supplying a power supply voltage to an internal circuit of the semiconductor chip, and a ground wiring layer in succession, and one of the first semiconductor chip and the second semiconductor chip further includes a second ground wiring layer or a second power supply wiring layer on a surface facing to the other semiconductor chip.
1. A three-dimensional integrated circuit comprising:
a first semiconductor chip; and
a second semiconductor chip stacked on the first semiconductor chip,
wherein the first semiconductor chip is provided with (i) a transistor layer, (ii) a first layer, which is one of a first power supply wiring layer and a first ground wiring layer, the first power supply wiring layer having a wiring pattern structure for stably supplying a power supply voltage to an internal circuit of the first semiconductor chip, and (iii) a second layer, which is the other one of the first power supply wiring layer and the first ground wiring layer,
wherein the first layer of the first semiconductor chip is located between (i) the transistor layer of the first semiconductor chip and (ii) the second layer of the first semiconductor chip,
wherein the second semiconductor chip is provided with (i) a transistor layer, (ii) a first layer, which is one of a second power supply wiring layer and a second ground wiring layer, the second power supply wiring layer having a wiring pattern structure for stably supplying a power supply voltage to an internal circuit of the second semiconductor chip, and (iii) a second layer, which is the other one of the second power supply wiring layer and the second ground wiring layer,
wherein the first layer of the second semiconductor chip is located between (i) the transistor layer of the second semiconductor chip and (ii) the second layer of the second semiconductor chip,
wherein the first semiconductor chip is further provided with a third layer, which is one of a third power supply wiring layer and a third ground wiring layer, the third layer of the first semiconductor chip being located (i) on a surface of the first semiconductor chip facing the second semiconductor chip and (ii) between the second layer of the first semiconductor chip and second semiconductor chip.
2. The three-dimensional integrated circuit according to claim 1 , further comprising a decoupling capacitor formed by a parasitic capacitance between (i) the third layer of the first semiconductor chip and (ii) the second layer of the second semiconductor chip.
3. The three-dimensional integrated circuit according to claim 1 , further comprising;
a first decoupling capacitor formed by a parasitic capacitance between (i) the first layer of the first semiconductor chip and (ii) the second layer of the first semiconductor chip; and
a second decoupling capacitor formed by a parasitic capacitance between (i) the first layer of the second semiconductor chip and (ii) the second layer of the second semiconductor chip.
4. The three-dimensional integrated circuit according to claim 1 , wherein the second semiconductor chip is stacked on the first semiconductor chip such that (i) the transistor layer, the first layer, the second layer, and the third layer of the first semiconductor chip face the transistor layer, the first layer, and the second layer of the second semiconductor chip and (ii) the transistor layer, the first layer, the second layer of the second semiconductor chip face the transistor layer, the first layer, the second layer, and the third layer of the first semiconductor chip.
5. The three-dimensional integrated circuit according to claim 1 ,
wherein the second layer the first semiconductor chip is provided immediately under the third layer of the first semiconductor chip, and
wherein the first semiconductor chip includes a decoupling capacitor formed by a parasitic capacitance between (i) the third layer of the first semiconductor chip and (ii) the second layer of the first semiconductor chip.
6. The three-dimensional integrated circuit according to claim 1 , wherein the wiring pattern structure of each of the first power supply wiring layer, the second power supply wiring layer, and the third power supply wiring layer includes mesh-like metal wiring.
7. The three-dimensional integrated circuit according to claim 1 , wherein the wiring pattern structure of each of the first power supply wiring layer, the second power supply wiring layer, and the third power supply wiring layer includes a power supply ring which encloses the wiring pattern structure and a strap which vertically or horizontally connects an inner surface of the power supply ring.
8. The three-dimensional integrated circuit according to claim 1 , wherein the transistor layer of the first semiconductor chip and the transistor layer of the second semiconductor chip are the same.
9. The three-dimensional integrated circuit according to claim 1 , wherein the first power supply wiring layer, the second power supply wiring layer, the third bower supply wiring layer, the first ground wiring layer, the second ground wiring lam and the third ground wiring layer correspond to global wiring layers.
10. The three-dimensional integrated circuit according to claim 1 , further comprising a substrate supporting the whole of the three-dimensional integrated circuit.
11. The three-dimensional integrated circuit according to claim 1 , further comprising a third semiconductor chip,
wherein the third semiconductor chip is stacked on one of the first semiconductor chip or the second semiconductor chip.
12. The three-dimensional integrated circuit according to claim 11 , further comprising a substrate supporting the whole of the three-dimensional integrated circuit,
wherein the third semiconductor chip is provided between the substrate and the one of the first semiconductor chip or the second semiconductor chip.
13. The three-dimensional integrated circuit according to claim 11 ,
wherein the first semiconductor chip or the second semiconductor chip is provided to be in contact with the substrate,
wherein the third semiconductor chip is provided on one of the first semiconductor chip and the second semiconductor chip which is not in contact with the substrate, and
wherein the first semiconductor chip or the second semiconductor chip which is provided to be in contact with the substrate consumes a higher current than the third semiconductor chip.
14. A processor device which includes the three-dimensional integrated circuit according to claim 1 .
15. The three-dimensional integrated circuit according to claim 1 ,
wherein the first layer of the first semiconductor chip is the first power supply wiring layer, and the second layer of the first semiconductor chip is the first ground wiring layer,
wherein the first layer of the second semiconductor chip is the second power supply wiring layer, and the second layer of the second semiconductor chip is the second ground wiring layer, and
wherein the second semiconductor chip is stacked on the first semiconductor chip such that (i) the transistor layer, the first layer, the second layer, and the third layer of the first semiconductor chip face the transistor layer, the first layer, and the second layer of the second semiconductor chip and (ii) the transistor layer, the first layer, the second layer of the second semiconductor chip face the transistor layer, the first layer, the second layer, and the third layer of the first semiconductor chip.
16. The three-dimensional integrated circuit according to claim 1 ,
wherein the first layer of the first semiconductor chip is the first ground wiring layer, and the second layer of the first semiconductor chip is the first power supply wiring layer,
wherein the first layer of the second semiconductor chip is the second ground wiring layer, and the second layer of the second semiconductor chip is the second power supply wiring layer, and
wherein the second semiconductor chip is stacked on the first semiconductor chip such that (i) the transistor layer, the first layer, the second layer, and the third layer of the first semiconductor chip face the transistor layer, the first layer, and the second layer of the second semiconductor chip and (ii) the transistor layer, the first layer, the second layer of the second semiconductor chip face the transistor layer, the first layer, the second layer, and the third layer of the first semiconductor chip.