Nanowire device with alumina passivation layer and methods of making same
In one aspect, the present disclosure relates to a device including a silicon substrate, wherein at least a portion of the substrate surface can be a silicon nanowire array; and a layer of alumina covering the silicon nanowire array. In some embodiments, the device can be a solar cell. In some embodiments, the device can be a p-n junction. In some embodiments, the p-n junction can be located below the bottom surface the nanowire array.
1. A process of manufacturing a photovoltaic cell comprising a nanowire array, comprising the steps of:
forming a nanowire array of p-type silicon nanowires on an n-type silicon substrate;
forming a p-n junction in the substrate below a bottom surface of the nanowire array; and
passivating the device by depositing a layer of alumina on the nanowire array by atomic layer deposition, the deposited layer resulting from no more than about 275 cycles with tetramethyl aluminum.
2. A device comprising:
a silicon substrate, wherein at least a portion of the substrate surface comprises a silicon nanowire array of p-type silicon nanowires; and
a layer of alumina covering and passivating the silicon nanowire array, the layer having a thickness of no more than about 275 atomic layers.
3. The device of claim 2 , wherein the device comprises a solar cell.
4. The device of claim 2 , wherein the device comprises a p-n junction.
5. The device of claim 4 , wherein the p-n junction is located below the bottom surface of the nanowire array.
6. A device comprising:
a silicon substrate, wherein at least a portion of the substrate surface comprises a black silicon with a surface including p-type silicon nanostructuring;
a layer of alumina covering and passivating the black silicon, the layer having a thickness of no more than about 275 atomic layers; and
a p-n junction located in the silicon substrate below a bottom surface of the nanostructuring.
7. The device of claim 6 , wherein the device comprises a solar cell.
8. The device of claim 6 , wherein the black silicon comprises an array of nanowires.
9. The device of claim 6 , wherein the black silicon comprises porous silicon.
10. The device of claim 6 , wherein the black silicon comprises silicon having a graded index of refraction.
11. The device of claim 6 , wherein the black silicon comprises silicon having a needle-shaped surface structure.
12. The process of claim 1 , wherein the nanowire array is passivated by the layer of alumina.
13. The process of claim 1 , wherein the nanowire array is doped p-type prior to step-b passivating the device.
14. The process of claim 1 , wherein forming the nanowire array comprises etching the nanowires into the substrate below a surface of the substrate.
15. The process of claim 1 , further comprising forming an electrical contact in electrical communication with the nanowire array on a surface of the substrate adjacent the nanowire array.
16. The device of claim 2 , further comprising an electrical contact in electrical communication with the nanowire array on the surface of the substrate adjacent the nanowie array.
17. The device of claim 2 , further comprising a p-n junction in the substrate below a bottom surface of the nanowire array.
18. The device of claim 6 , further comprising an electrical contact in electrical communication with the nanowire array on the surface of the substrate adjacent the nanowire array.