Method for code evaluation using ISI ratio
An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the “ISI Ratio” are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.
1. A method comprising:
receiving a set of information bits;
generating a reduced-alphabet codeword vector with an encoder by forming a weighted sum of sub-channel code vectors wherein a weighting of each sub-channel code vector is based in part on a corresponding antipodal weight determined by a corresponding information bit in the set of received bits, and wherein the sub-channel code vectors form a reduced-alphabet weight matrix, and are mutually orthogonal and orthogonal to a common mode vector; and,
transmitting the reduced-alphabet codeword vector using a plurality of line drivers, wherein the reduced-alphabet codeword vector comprises a plurality of reduced-alphabet codeword vector elements, and each reduced-alphabet codeword vector element is transmitted on a wire of a multi-wire communication bus by a respective one of the plurality of line drivers.
2. The method of claim 1 wherein the encoder is an orthogonal encoding logic circuit, and wherein generating a reduced-alphabet codeword vector comprises mapping the received set of information bits to a respective reduced-alphabet codeword vector and outputting a reduced-alphabet codeword vector selector signal.
3. The method of claim 2 wherein the reduced-alphabet codeword vector selector signal is provided to the plurality of line drivers, and wherein each line driver of the plurality of line drivers uses a portion of the reduced-alphabet codeword vector selector signal to output a corresponding a current or voltage representing the reduced-alphabet codeword vector element.
4. The method of claim 1 wherein at least one of the sub-channel code vectors has a non-normalized magnitude and wherein the row-wise linear combinations of the reduced-alphabet provide a reduced alphabet.
5. The method of claim 1 , wherein the reduced-alphabet codeword vector elements are selected from the normalized set of elements {+1, +⅓, −⅓, −1}.
6. The method of claim 1 wherein there are five sub-channel vectors, and the multi-wire communication bus comprises six wires.
7. The method of claim 1 wherein the antipodal weights are selected from the normalized set of elements {+1, −1}.
8. The method of claim 1 wherein an antipodal weight of at least one sub-channel is modulated according to a clock signal.
9. The method of claim 1 wherein a non-modulated common mode sub-channel vector is included to provide a voltage offset.
10. The method of claim 1 wherein sub-channel code vectors having three non-zero elements comprise a first non-zero element twice as large as each of a second non-zero element and a third non-zero element, and a position of the first non-zero element is aligned to where only one other sub-channel codeword vector has a non-zero element.
11. An apparatus comprising:
a plurality of signal conductors for receiving a set of information bits;
an encoder connected to the signal conductors for generating a reduced-alphabet codeword vector by forming a sum of sub-channel code vectors wherein a weighting of each sub-channel code vector is based in part on a corresponding antipodal weight determined by a corresponding information bit in the set of received bits, and wherein the sub-channel code vectors form a reduced-alphabet weight matrix, and are mutually orthogonal and orthogonal to a common mode vector; and
a plurality of line drivers for transmitting the reduced alphabet codeword vector, wherein the reduced-alphabet codeword vector comprises a plurality of reduced-alphabet codeword vector elements, and each reduced-alphabet codeword vector element is transmitted on a wire of a multi-wire communication bus by a respective one of the plurality of line drivers.
12. The apparatus of claim 11 , wherein the encoder further comprises a logic circuit that maps the received set of information bits to a respective reduced-alphabet codeword vector and outputs a reduced-alphabet codeword vector selector signal.
13. The apparatus of claim 12 , further comprising wire connections for providing the reduced-alphabet codeword vector selector signal to the plurality of line drivers, wherein each line driver of the plurality of line drivers uses a portion of the reduced-alphabet codeword vector selector signal to output a corresponding a current or voltage representing the reduced-alphabet codeword vector element.
14. The apparatus of claim 11 , wherein the encoder is configured to produce a reduced-alphabet comprising a set of elements {+1, +⅓, −⅓, −1}.
15. The apparatus of claim 14 , wherein the multi-wire communications bus comprises six wires to transmit a set of five sub-channel code vectors.
16. The apparatus of claim 11 , wherein the encoder is configured to select the antipodal weights from a set of elements {+1,−1}.
17. The apparatus of claim 11 , wherein the encoder is configured to modulate at least one sub-channel code vector according to a clock signal.
18. The apparatus of claim 11 , wherein the encoder is configured to provide a voltage offset by providing a non-modulated common mode sub-channel vector.