High electron mobility transistor and method of forming the same
A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature.
1. A high electron mobility transistor (HEMT) comprising:
a first III-V compound layer;
a second III-V compound layer on the first III-V compound layer and different from the first III-V compound layer in composition, wherein a carrier channel is located in the first III-V compound layer along an interface between the first III-V compound layer and the second first III-V compound layer;
a cap layer over the second III-V layer;
a salicide source feature and a salicide drain feature in contact with the first III-V compound layer through the second III-V compound layer, wherein at least one of the silicide source feature or the silicide drain feature extends along a top portion of the cap layer; and
a gate electrode over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature.
2. The HEMT of claim 1 , wherein each of the salicide source feature and the salicide drain feature comprises silicon and a metal including at least one of Ti, Co, Ni, W, Pt, Ta, Pd or Mo.
3. The HEMT of claim 1 , wherein each of the salicide source feature and the salicide drain feature contacts the carrier channel.
4. The HEMT of claim 1 further comprising an ohmic metal unit on each of the salicide source feature and the salicide drain feature.
5. The HEMT of claim 4 , wherein the ohmic metal unit comprises Al, Ti, Cu, Mo, Ti or Ni.
6. The HEMT of claim 4 , wherein the ohmic metal unit is at least partially embedded in each of the salicide source feature and the salicide drain feature.
7. The HEMT of claim 1 , wherein each of the salicide source feature and the salicide drain feature is at least partially embedded in the second III-V compound layer and a portion of the first III-V compound layer.
8. The HEMT of claim 1 , wherein each of the salicide source feature and the salicide drain feature has a concave top surface.
9. The HEMT of claim 1 , wherein the gate electrode comprises titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), titanium tungsten nitride (TiWN), tungsten (W) or tungsten nitride (WN).
10. The HEMT of claim 1 further comprising a region configured to deplete a portion of the carrier channel, wherein the region is under the gate electrode and above the first III-V compound layer.
11. The HEMT of claim 1 , wherein the at least one of the silicide source feature or the silicide drain feature is in direct contact with the cap layer.
12. A high electron mobility transistor (HEMT) comprising:
a gallium nitride (GaN) layer on a substrate;
an aluminum gallium nitride (AlGaN) layer on the GaN layer;
a salicide source feature and a salicide drain feature spaced apart and at least partially embedded in the AlGaN layer, wherein each of the salicide source feature and the salicide drain feature has a concave top surface;
a gate electrode over a portion of the AlGaN layer between the salicide source feature and the salicide drain feature; and
an ohmic unit on each of the silicide source feature and the silicide drain feature; and
a protection layer extending along sidewalls and a top surface of the ohmic unit.
13. The HEMT of claim 12 , wherein a carrier channel is located between the GaN layer and the AlGaN layer, the carrier channel comprising a depletion region under the gate electrode.
14. The HEMT of claim 12 , wherein each of the salicide source feature and the salicide drain feature has a top width larger than a bottom width.
15. The HEMT of claim 12 , wherein each of the salicide source feature and the salicide drain feature comprises silicon and a metal including at least one of Ti, Co, Ni, W, Pt, Ta, Pd or Mo.
16. The HEMT of claim 12 , wherein each of the salicide source feature and the salicide drain feature contacts a carrier channel located between the GaN layer and the AlGaN layer.
17. The HEMT of claim 12 , wherein the ohmic unit is free of Au and comprises Al, Ti, Cu, Mo, Ti or N.
18. The HEMT of claim 16 , wherein the ohmic unit is at least partially embedded in each of the salicide source feature and the salicide drain feature.
19. The HEMT of claim 16 , wherein a bottom surface of the ohmic unit is lower than a top surface of the AlGaN layer.
20. A high electron mobility transistor (HEMT) comprising:
a channel layer;
a donor-supply layer on the channel layer and different from the channel layer in composition;
a salicide source feature and a salicide drain feature in contact with the channel layer through the donor-supply layer;
a gate electrode over a portion of the donor-supply layer between the salicide source feature and the salicide drain feature; and
a carrier depletion layer between the gate electrode and the donor-supply layer, wherein the carrier depletion layer contains point defects.