Method of fabricating a ferroelectric capacitor
Ferroelectric capacitors used in ferroelectric random access memories (F-RAM) and methods for fabricating the same to reduce sidewall leakage are described. In one embodiment, the method includes depositing over a surface of a substrate, a ferro stack including a bottom electrode layer electrically coupled to a bottom electrode contact extending through the substrate, a top electrode layer and ferroelectric layer there between. A hard-mask is formed over the ferro stack, and a top electrode formed by etching through the top electrode layer and at least partially through the ferroelectric layer. A non-conductive barrier is formed on sidewalls formed by etching through the top electrode layer and at least partially through the ferroelectric layer, and then a bottom electrode is formed by etching the bottom electrode layer so that conductive residues generated by the etching are electrically isolated from the top electrode by the non-conductive barrier.
1. A method comprising:
depositing a ferro stack over a surface of a substrate, the ferro stack including a bottom electrode layer electrically coupled to a bottom electrode contact extending through the substrate, a top electrode layer and ferroelectric layer there between;
forming a hard-mask over the ferro stack;
forming a ferroelectric capacitor, wherein forming the ferroelectric capacitor comprises:
etching through the top electrode layer and at least partially through the ferroelectric layer to form a top electrode;
forming a non-conductive barrier deposited directly on a top surface and sidewalls of the ferroelectric capacitor formed by etching through the top electrode layer and at least partially through the ferroelectric layer;
forming a first patterned photoresist over a portion of the non-conductive barrier located on the top surface of the ferroelectric capacitor and not the sidewalls;
etching the non-conductive barrier using the first patterned photoresist to expose a surface of a bottom electrode layer; and
forming a bottom electrode, wherein forming the bottom electrode comprises etching the bottom electrode layer using the non-conductive barrier as a mask, and wherein conductive residues generated by the etching of the bottom electrode layer are electrically isolated from the top electrode by the non-conductive barrier that covers the sidewalls and the top surface of the ferroelectric capacitor,
wherein the ferro stack further comprises a conductive oxygen (O 2 ) barrier layer deposited on the surface of the substrate between the substrate and the bottom electrode layer, and further comprises etching the conductive O 2 barrier layer to form an O 2 barrier, wherein the bottom electrode is electrically coupled to the bottom electrode contact through the O 2 barrier, and wherein a thickness of the non-conductive barrier on the sidewalls of the ferroelectric capacitor is reduced while etching the bottom electrode layer and the conductive O 2 barrier layer.
2. The method of claim 1 further comprising encapsulating the ferroelectric capacitor with a hydrogen (H 2 ) barrier.
3. The method of claim 2 wherein the H 2 barrier comprises a multi-layer H 2 barrier.
4. The method of claim 1 wherein the etching the conductive O 2 barrier layer further comprises forming a local interconnect on the surface of the substrate.
5. The method of claim 1 wherein the non-conductive barrier comprises lead zirconate titanate (PZT).
6. The method of claim 1 wherein the bottom electrode is electrically coupled through the O 2 barrier to a bottom electrode contact extending through the substrate.
7. The method of claim 1 wherein etching the bottom electrode layer comprises etching the bottom electrode layer with an etch chemistry highly selective to a material of the non-conductive barrier.
8. The method of claim 1 wherein the bottom electrode layer comprises iridium (Ir).
9. The method of claim 1 wherein the conductive O 2 barrier layer comprises titanium aluminum nitride (TiAlN).