IP Library Granted Patent US 9,112,593
Granted Patent B1
US 9,112,593 · App. 14/621,037 · Granted Aug 18, 2015

Apparatus and method for compensating for timing offset in spread spectrum system

Inventors: Jin Soup Joung (Gyeonggi-do, KR); Sung Chan Choi (Gyeonggi-do, KR); Yong Hoon Lim (Seoul, KR); Chang Woo Seo (Gyeonggi-do, KR)
Assignee: INNOWIRELESS CO., LTD.
H04B1/7075
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Quick Facts
Patent No.
US 9,112,593
App. No.
14/621,037
Granted
Aug 18, 2015
Kind
B1
Abstract

An apparatus and method for compensating for a timing offset in a spread spectrum system which perform an oversampling of respective symbols to obtain a plurality of samples, estimate a chip clock timing offset and a symbol clock timing offset from the plurality of samples, and compensate for the chip clock timing offset and the symbol clock timing offset.

Claims (302)

1. An apparatus for compensating for a timing offset in a spread spectrum system, the apparatus comprising:

an oversampling unit configured to oversample, by a multiple P, data whose each of N symbols is spread over and received by C chips;

an oversampled chip collection unit configured to collect C, which is a number of chips, samples at positions apart from each of all the oversampled samples by the multiple P, which is the oversampling multiple;

a despreading unit configured to despread each of collected oversampled chips using a unique code of a corresponding symbol;

a peak value detection/storage unit configured to detect an oversampled chip having a largest correlation value among despread oversampled chips in every predetermined section, and then store sample indices of the detected oversampled chips as peak value sample indices;

a timing offset calculation unit configured to calculate a chip clock timing offset O ct and a system clock timing offset O st using the respective peak value sample indices; and

a downsampling unit configured to downsample the oversampled samples while compensating for the chip clock timing offset and the system clock timing offset.

2. The apparatus of claim 1 , wherein the predetermined section is C*P samples.

3. The apparatus of claim 1 , wherein the chip clock timing offset O ct and the system clock timing offset O st are calculated based on a number of samples between a peak value sample index of each symbol and a peak value sample index of a first symbol.

4. The apparatus of claim 3 , wherein the chip clock timing offset O ct is calculated using an equation below:

O ct ( n )= C cto *n ( n is a symbol index),

where the chip clock timing offset coefficient C cto is calculated using an equation below:

C

cto

=

N

*

δ

-

β

*

α

N

*

γ

-

β

*

β

,

and

the system clock timing offset coefficient O st is calculated using an equation below:

O

st

=

α

*

δ

-

β

*

δ

N

*

γ

-

β

*

β

,

where d[n]=q[n]−q[0] (n=0, 1, . . . , N−1), e n =d[n]−n*P*C (n=0, 1, . . . , N−1),

α

=

n

=

0

N

-

1

e

n

,

β

=

n

=

0

N

-

1

n

=

N

*

(

N

-

1

)

2

,

γ

=

n

=

0

N

-

1

n

2

=

N

*

(

N

-

1

)

*

(

2

N

-

1

)

6

,

δ

=

n

=

0

N

-

1

(

e

n

*

n

)

,

q[0] denotes the peak value sample index of the first symbol, and q[n] denotes a peak value sample index of an n th symbol.

5. The apparatus of claim 4 , wherein a downsampling time t ds is calculated using an equation below:

t ds =n*P*C+P*c+C cto *n+O st ( n is a symbol index, and c is a chip index).

6. The apparatus of claim 1 , wherein a downsampled sample value V ds is calculated using an equation below:

V ds =V I *(1− F )+( V I+1 )* F ( I is an integer part of t ds , and F is a decimal part of t ds )

where V ds denotes a downsampled sample value compensated at the downsampling time t ds , and V I and V I+1 denote sample values downsampled at a time corresponding to the integer part I of the downsampling time t ds and a time corresponding to a sum of the integer part I and one (I+1), respectively.

7. A method of compensating for a timing offset in a spread spectrum system, the method comprising:

oversampling, by a multiple P, data whose each of N symbols is spread over and received by C chips;

collecting C, which is a number of chips, samples at positions apart from each of all the oversampled samples by the multiple P, which is the oversampling multiple;

despreading each of collected oversampled chips using a unique code of a corresponding symbol;

detecting an oversampled chip having a largest correlation value among despread oversampled chips in every predetermined section, and then storing sample indices of the detected oversampled chips as peak value sample indices;

calculating a chip clock timing offset O ct and a system clock timing offset O st using the respective peak value sample indices; and

downsampling the oversampled samples while compensating for the chip clock timing offset and the system clock timing offset.

8. The method of claim 7 , wherein the predetermined section is C*P samples.

9. The method of claim 7 , wherein the chip clock timing offset O ct and the system clock timing offset O st are calculated based on a number of samples between a peak value sample index of each symbol and a peak value sample index of a first symbol.

10. The method of claim 9 , wherein the chip clock timing offset O ct is calculated using an equation below:

O ct ( n )= C cto *n ( n is a symbol index),

where the chip clock timing offset coefficient C cto is calculated using an equation below:

C

cto

=

N

*

δ

-

β

*

α

N

*

γ

-

β

*

β

,

and

the system clock timing offset coefficient O st is calculated using an equation below:

O

st

=

α

*

δ

-

β

*

δ

N

*

γ

-

β

*

β

,

where d[n]=q[n]−q[0] (n=0, 1, . . . , N−1), e n =d[n]−n*P*C (n=0, 1, . . . , N−1),

α

=

n

=

0

N

-

1

e

n

,

β

=

n

=

0

N

-

1

n

=

N

*

(

N

-

1

)

2

,

γ

=

n

=

0

N

-

1

n

2

=

N

*

(

N

-

1

)

*

(

2

N

-

1

)

6

,

δ

=

n

=

0

N

-

1

(

e

n

*

n

)

,

q[0] denotes the peak value sample index of the first symbol, and q[n] denotes a peak value sample index of an n th symbol.

11. The method of claim 10 , wherein a downsampling time t ds is calculated using an equation below:

t ds =n*P*C+P*c+C cto *n+O st ( n is a symbol index, and c is a chip index).

12. The method of claim 7 , wherein a downsampled sample value V ds is calculated using an equation below:

V ds =V I *(1− F )+( V I+1 )* F ( I is an integer part of t ds , and F is a decimal part of t ds )

where V ds denotes a downsampled sample value compensated at the downsampling time t ds , and V I and V I+1 denote sample values downsampled at a time corresponding to the integer part I of the downsampling time t ds and a time corresponding to a sum of the integer part I and one (I+1), respectively.

Assignments (2)
CHANGE OF NAME Recorded Jul 17, 2026
From: INNOWIRELESS CO., LTD.
To: LIG ACCUVER CO., LTD.
Reel/Frame 076001/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2015
From: JOUNG, JIN SOUP; CHOI, SUNG CHAN; LIM, YONG HOON; SEO, CHANG WOO
To: INNOWIRELESS CO., LTD.
Reel/Frame 035055/0494 →
Priority Claims (1)
KR 10-2015-0003584 · Jan 9, 2015 · national