Semiconductor device and method for manufacturing the same
A semiconductor device and a method for manufacturing the same are disclosed, which can improve device characteristics by increasing a process margin between an active region and a storage node contact. The semiconductor device includes an active region, a device isolation film formed to have a lower height than the active region, and exposing an upper part of the active region, and a barrier pattern formed at a sidewall of the exposed active region of an upper part of the device isolation film.
1. A semiconductor device comprising:
first and second active regions that are adjacent to each other;
a device isolation region disposed between the first and the second active regions and including a barrier pattern, wherein the barrier pattern is disposed laterally on sidewalls of an upper portion of the first active region;
a bit line contact coupled to the first active region; and a storage node contact coupled to the second active region,
wherein the device isolation region is disposed in a substrate, and
wherein the device isolation region is formed of a single device isolation film, and the barrier pattern is a protruding portion of the device isolation film.
2. The semiconductor device of claim 1 ,
wherein a top surface of the first active region is disposed at a first level, and
wherein a top surface of the device isolation region is disposed at a second level lower than the first level.
3. The semiconductor device of claim 2 ,
wherein the barrier pattern extends up to the first level.
4. The semiconductor device of claim 1 ,
wherein the storage node contact extends from the second active region over the device isolation region.
5. The semiconductor device of claim 2 ,
wherein a top surface of the second active region is disposed at substantially the same level as the top surface of the first active region.
6. The semiconductor device of claim 2 ,
wherein a bottom of the storage node contact is lower than the first level.
7. The semiconductor device of claim 1 , the device further comprising:
a third active region adjacent to the first active region;
a second device isolation region between the first and the third active regions;
a second storage node contact coupled to the third active region; and
a second barrier pattern extending from the second device isolation region to a region between the first active region and the second storage node contact.
8. A semiconductor device comprising:
first and second active regions that are adjacent to each other;
a device isolation region provided between the first and the second active regions, wherein the device isolation region includes an upper step and a lower step, wherein a top surface of the upper step is level with a top surface of the first active region, the upper step being proximate to the first active region, the lower step being proximate to the second active region;
a bit line contact coupled to the first active region; and
a storage node contact coupled to the second active region and further coupled to the lower step of the device isolation region,
wherein the device isolation region is disposed in a substrate and formed of a single device isolation film.