IP Library Granted Patent US 9,123,780
Granted Patent B2
US 9,123,780 · App. 13/720,346 · Granted Sep 1, 2015

Method and structures for heat dissipating interposers

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,123,780
App. No.
13/720,346
Granted
Sep 1, 2015
Kind
B2
Abstract

A method for making an interconnect element includes depositing a thermally conductive layer on an in-process unit. The in-process unit includes a semiconductor material layer defining a surface and edges surrounding the surface, a plurality of conductive elements, each conductive element having a first portion extending through the semiconductor material layer and a second portion extending from the surface of the semiconductor material layer. Dielectric coatings extend over at least the second portion of each conductive element. The thermally conductive layer is deposited on the in-process unit at a thickness of at least 10 microns so as to overlie a portion of the surface of the semiconductor material layer between the second portions of the conductive elements with the dielectric coatings positioned between the conductive elements and the thermally conductive layer.

Claims (26)

1. A method for making an interconnect element, comprising:

depositing a thermally conductive layer on an in-process unit, the in-process unit including a semiconductor material layer defining a surface and edges surrounding the surface, a plurality of conductive elements, each conductive element having a first portion extending through the semiconductor material layer, a second portion extending from the surface of the semiconductor material layer, and dielectric coatings extending over at least the second portion of each conductive element, each of the conductive elements further including an edge surface and a end surface, the end surface being spaced apart from the surface of the semiconductor material layer,

wherein the thermally conductive layer is deposited on the in-process unit at a thickness of at least 10 microns so as to overlie a portion of the surface of the semiconductor material layer between the second portions of the conductive elements with the dielectric coatings positioned between the conductive elements and the thermally conductive layer, and

wherein the thermally conductive layer is deposited to extend along respective edge surfaces and end surfaces of the plurality of conductive elements, and wherein the method further includes removing a portion of the thermally conductive layer that extends along the end surface to expose the end surface at a surface of the thermally conductive layer.

2. The method of claim 1 , wherein the thermally conductive layer is further deposited to overlie the surface of the semiconductor material in a location adjacent to at least one edge of the semiconductor material layer.

3. The method of claim 1 , further including, prior to depositing the thermally conductive layer, removing a portion of the semiconductor material layer to expose the edge surfaces of the conductive elements and to define the surface of the semiconductor layer such that portions of the conductive elements extend away therefrom.

4. The method of claim 1 , further including, prior to the step of depositing the thermally conductive layer, depositing a barrier layer over at least the surface of the semiconductor material layer, wherein the thermally conductive layer is deposited over the barrier layer such that the barrier layer electrically insulates the semiconductor material layer from the thermally conductive layer.

5. The method of claim 1 , wherein depositing the thermally conductive layer includes depositing copper and wherein the thermally conductive layer is deposited having a thickness of 10-300 microns.

6. The method of claim 1 , wherein depositing the thermally conductive layer includes depositing a highly thermally conductive material of one of graphite and carbon, and wherein the thermally conductive layer is deposited at a thickness of 10-200 microns.

7. The method of claim 1 , further including depositing a patternable material layer over the surface of the semiconductor material layer and patterning the patternable material layer to form a plurality of spacers extending in at least one lateral direction along the surface of the semiconductor material layer prior to depositing the thermally conductive layer, and wherein the thermally conductive layer is deposited in a plurality of sections with respective ones of the spacers therebetween.

8. The method of claim 1 , further including removing portions of the thermally conductive layer to form a plurality of gaps extending in at least one lateral direction over the surface of the semiconductor material layer, the gaps being between respective sections of the thermally conductive layer.

9. A method for making an interconnect element, comprising:

depositing a thermally conductive layer on an in-process unit, the in-process unit including a semiconductor material layer defining a surface and edges surrounding the surface, a plurality of conductive elements, each conductive element having a first portion extending through the semiconductor material layer and a second portion extending from the surface of the semiconductor material layer, and dielectric coatings extending over at least the second portion of each conductive element;

removing portions of the thermally conductive layer to form a plurality of gaps extending in at least one lateral direction over the surface of the semiconductor material layer, the gaps being between respective sections of the thermally conductive layer; and

depositing a compliant material within at least portions of at least one of the gaps,

wherein the thermally conductive layer is deposited on the in-process unit at a thickness of at least 10 microns so as to overlie a portion of the surface of the semiconductor material layer between the second portions of the conductive elements with the dielectric coatings positioned between the conductive elements and the thermally conductive layer.

10. The method of claim 9 , wherein the thermally conductive layer is further deposited to overlie the surface of the semiconductor material in a location adjacent to at least one edge of the semiconductor material layer.

11. The method of claim 9 , further including, prior to depositing the thermally conductive layer, removing a portion of the semiconductor material layer to expose the edge surfaces of the conductive elements and to define the surface of the semiconductor layer such that portions of the conductive elements extend away therefrom.

12. The method of claim 9 , further including, prior to the step of depositing the thermally conductive layer, depositing a barrier layer over at least the surface of the semiconductor material layer, wherein the thermally conductive layer is deposited over the barrier layer such that the barrier layer electrically insulates the semiconductor material layer from the thermally conductive layer.

13. The method of claim 9 , wherein depositing the thermally conductive layer includes depositing copper and wherein the thermally conductive layer is deposited having a thickness of 10-300 microns.

14. The method of claim 9 , wherein depositing the thermally conductive layer includes depositing a highly thermally conductive material of one of graphite and carbon, and wherein the thermally conductive layer is deposited at a thickness of 10-200 microns.

15. The method of claim 9 , wherein each conductive element further has an edge surface and an end surface, the end surface being spaced apart from the surface of the semiconductor material layer, and wherein the thermally conductive layer is further deposited to extend over respective edge surfaces of the conductive elements.

16. The method of claim 15 , wherein the thermally conductive layer is deposited over the edge surface and end surface of the conductive element, and wherein the method further includes removing a portion of the thermally conductive layer that overlies the end surface to expose the end surface at a surface of the thermally conductive layer.

17. The method of claim 9 , further including depositing a patternable material layer over the surface of the semiconductor material layer and patterning the patternable material layer to form a plurality of spacers extending in at least one lateral direction along the surface of the semiconductor material layer prior to depositing the thermally conductive layer, and wherein the thermally conductive layer is deposited in a plurality of sections with respective ones of the spacers therebetween.

18. The method of claim 9 , further comprising forming the gaps to extend entirely through the thermally conductive layer.

19. The method of claim 15 , wherein the thermally conductive layer is deposited along the respective edge surfaces of the conductive element.

Assignments (6)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0661 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073689/0793 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2013
From: UZOH, CYPRIAN EMEKA; MONADGEMI, PEZHMAN; CASKEY, TERRENCE; AYATOLLAHI, FATIMA LINA; HABA, BELGACEM; WOYCHIK, CHARLES G.; NEWMAN, MICHAEL
To: INVENSAS CORPORATION
Reel/Frame 030678/0402 →