Vertical trench MOSFET device in integrated power technologies
A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures. The deep trench structures include dielectric liners. The deep trench structures are spaced so as to form RESURF regions for the drift region. Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions. A body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners.
1. A semiconductor device, comprising:
a substrate comprising a semiconductor having a first conductivity type; and
a vertical drain extended metal oxide semiconductor (MOS) transistor, including:
a plurality of deep trench structures disposed in said substrate, at least one micron deep, each having a dielectric liner abutting said substrate, said deep trench structures having substantially equal depths;
a vertical drain contact region having a second conductivity type opposite from said first conductivity type disposed in said substrate, said vertical drain contact region abutting and being bounded on at least two opposite sides by a portion of said deep trench structures;
a vertically oriented drift region having said second conductivity type disposed in said substrate, abutting and being bounded on at least two opposite sides by a portion of said deep trench structures, in which said vertically oriented drift region makes electrical connection to said vertical drain contact region proximate to a bottom of a first deep trench structure of said plurality of said deep trench structures, said first deep trench structure separating said vertically oriented drift region from said vertical drain contact region;
a vertical gate on a gate dielectric layer disposed in a vertically oriented gate trench in said dielectric liner of a first deep trench structure of said plurality of deep trench structures; and
a body region having said first conductivity type disposed over said vertically oriented drift region and contacting said gate dielectric layer, such that said vertical gate extends below said body region.
2. The semiconductor device of claim 1 , in which said vertical gate does not extend laterally into a curved portion of said dielectric liner.
3. The semiconductor device of claim 1 , in which said vertical gate extends laterally into a curved portion of said dielectric liner.
4. The semiconductor device of claim 1 , in which:
said vertically oriented drift region is a first vertically oriented drift region;
said vertical gate is a first vertical gate;
said gate dielectric layer is a first gate dielectric layer;
said vertically oriented gate trench is a first vertically oriented gate trench; and
said vertical drain extended MOS transistor further includes a second vertically oriented drift region separated from said first vertically oriented drift region by a first deep trench structure of said plurality of said deep trench structures, with a second vertical gate on a second gate dielectric layer disposed in a second vertically oriented gate trench in said dielectric liner of said first deep trench structure.
5. The semiconductor device of claim 1 , in which said deep trench structure is 2.5 microns to 5 microns deep.
6. The semiconductor device of claim 1 , in which:
said first conductivity type is p-type; and
said second conductivity type is n-type.
7. A semiconductor device, comprising:
a substrate comprising a semiconductor having a first conductivity type; and
a vertical drain extended metal oxide semiconductor (MOS) transistor, including:
a plurality of deep trench structures disposed in said substrate, at least one micron deep, each having a dielectric liner abutting said substrate, said deep trench structures having substantially equal depths;
a vertical drain contact region having a second conductivity type opposite from said first conductivity type disposed in said substrate, said vertical drain contact region abutting and being bounded on at least two opposite sides by a portion of said deep trench structures;
a vertically oriented drift region having said second conductivity type disposed in said substrate, abutting and being bounded on at least two opposite sides by a portion of said deep trench structures;
a vertical gate on a gate dielectric layer disposed in a vertically oriented gate trench in said dielectric liner of a first deep trench structure of said plurality of deep trench structures; and
a body region having said first conductivity type disposed over said vertically oriented drift region and contacting said gate dielectric layer, such that said vertical gate extends below said body region, in which said vertical drain extended MOS transistor further includes a buried layer having said second conductivity type disposed in said substrate, extending under said vertically oriented drift region and making electrical connection to said vertical drain contact region.
8. The semiconductor device of claim 7 , in which said vertical gate does not extend laterally into a curved portion of said dielectric liner.
9. The semiconductor device of claim 7 , in which said vertical gate extends laterally into a curved portion of said dielectric liner.
10. The semiconductor device of claim 7 , in which said deep trench structure is 2.5 microns to 5 microns deep.
11. The semiconductor device of claim 7 , in which:
said first conductivity type is p-type; and
said second conductivity type is n-type.
12. A semiconductor device, comprising:
a substrate comprising a semiconductor having a first conductivity type; and
a vertical drain extended metal oxide semiconductor (MOS) transistor, including:
a plurality of deep trench structures disposed in said substrate, at least one micron deep, each having a dielectric liner abutting said substrate, said deep trench structures having substantially equal depths;
a vertical drain contact region having a second conductivity type opposite from said first conductivity type disposed in said substrate, said vertical drain contact region abutting and being bounded on at least two opposite sides by a portion of said deep trench structures;
a vertically oriented drift region having said second conductivity type disposed in said substrate, abutting and being bounded on at least two opposite sides by a portion of said deep trench structures;
a vertical gate on a gate dielectric layer disposed in a vertically oriented gate trench in said dielectric liner of a first deep trench structure of said plurality of deep trench structures; and
a body region having said first conductivity type disposed over said vertically oriented drift region and contacting said gate dielectric layer, such that said vertical gate extends below said body region, in which said vertically oriented drift region is laterally surrounded by a first deep trench structure of said plurality of said deep trench structures, said first deep trench structure having a closed loop configuration.
13. The semiconductor device of claim 12 , in which said vertical gate laterally surrounds said vertically oriented drift region.
14. The semiconductor device of claim 12 , in which said vertical gate does not extend laterally into a curved portion of said dielectric liner.
15. The semiconductor device of claim 12 , in which said vertical gate extends laterally into a curved portion of said dielectric liner.
16. The semiconductor device of claim 12 , in which said deep trench structure is 2.5 microns to 5 microns deep.
17. The semiconductor device of claim 12 , in which:
said first conductivity type is p-type; and
said second conductivity type is n-type.