IP Library › Granted Patent US 9,128,502
Granted Patent B2
US 9,128,502 · App. 13/961,852 · Granted Sep 8, 2015

Analog switch for RF front end

Inventors: James Francis Imbornone (Boxborough, MA); Xinwei Wang (Dunstable, MA); Zhenying Luo (Boxborough, MA); Xiangdong Zhang (Westford, MA)
Assignee: Qualcomm Incorporated
G05F1/461H03K17/063H03K2017/066H03K2217/0018H03K2217/0054
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Quick Facts
Patent No.
US 9,128,502
App. No.
13/961,852
Granted
Sep 8, 2015
Kind
B2
Abstract

Techniques for improving the linearity of radio-frequency (RF) front-end switches. In an aspect, open-loop techniques are disclosed for superimposing the output voltage of one or more negative rectifiers on a negative substrate bias voltage to reduce the non-linearities associated with voltage-dependent substrate leakage current. In another aspect, closed-loop techniques are further disclosed for maintaining the substrate bias voltage close to a reference voltage. Exemplary embodiments of the circuit blocks are further described.

Claims (36)

1. An apparatus comprising:

a transistor having a substrate; and

a negative rectifier configured to rectify a negative portion of a voltage related to a drain-to-source voltage of the transistor,

the substrate coupled via a first resistor to a constant bias voltage and coupled via a second resistor to an output of the negative rectifier.

2. The apparatus of claim 1 , further comprising a gain element configured to generate the voltage related to the drain-to-source voltage of the transistor as a gain voltage proportional to the drain-to-source voltage of the transistor.

3. The apparatus of claim 2 , the gain element comprising a series resistive divider, wherein at least one resistor of the series resistive divider has an adjustable resistance.

4. The apparatus of claim 2 , further comprising:

closed-loop circuitry for adjusting a gain of the gain element such that a substrate bias voltage of the transistor is approximately equal to a reference voltage.

5. The apparatus of claim 4 , the closed-loop circuitry comprising:

a low-pass filter coupled to the substrate bias voltage; and

operational amplifier circuitry having a first input coupled to the low-pass filter and having a second input coupled to the reference voltage, wherein the operational amplifier circuitry is coupled to a resistor in the gain element that has an adjustable resistance.

6. The apparatus of claim 2 , the gain element comprising a capacitive divider.

7. The apparatus of claim 1 , the negative rectifier comprising a negative diode rectifier.

8. The apparatus of claim 7 , the negative diode rectifier comprising a negative voltage doubler.

9. The apparatus of claim 1 , further comprising a plurality of transistors coupled in series with the transistor, wherein each of the plurality of transistors is coupled to the negative rectifier.

10. The apparatus of claim 9 , wherein gates of the plurality of transistors are coupled to a negative bias voltage.

11. An apparatus comprising:

means for rectifying a negative portion of a voltage related to a drain-to-source voltage of a transistor to generate a rectified voltage;

means for coupling the rectified voltage to a substrate of the transistor;

means for generating the voltage related to the drain-to-source voltage of the transistor as a voltage proportional to the drain-to-source voltage of the transistor; and

means for adjusting the voltage proportional to the drain-to-source voltage to maintain a constant rectified voltage.

12. The apparatus of claim 11 , the means for rectifying the negative portion comprising means for coupling the voltage proportional to the drain-to-source voltage to a negative voltage doubler.

13. The apparatus of claim 12 , the means for rectifying the negative portion further comprising a negative diode rectifier.

14. A method comprising:

rectifying a negative portion of a voltage proportional to a drain-to-source voltage of a transistor to generate a rectified voltage; and

coupling the rectified voltage via a first resistor to a substrate of the transistor, wherein the substrate of the transistor is coupled via a second resistor to a constant bias voltage.

15. The method of claim 14 , wherein rectifying the negative portion comprises coupling the voltage proportional to the drain-to-source voltage to a negative voltage doubler.

16. The apparatus of claim 7 , the negative diode rectifier comprising:

an input terminal;

an output terminal;

a capacitor coupled to ground and coupled to the output terminal;

a resistor coupled to ground and coupled to the output terminal; and

a diode coupled to the input terminal and coupled to the output terminal.

17. The apparatus of claim 1 , wherein the transistor is included in a shunt switch configured to ground voltages associated with an inactive signal path of a transceiver.

18. The apparatus of claim 17 , wherein the inactive signal path is tuned to a first frequency band of a plurality of frequency bands.

19. The apparatus of claim 11 , wherein the means for adjusting the voltage proportional to the drain-to-source voltage of the transistor maintains a substantially constant rectified voltage.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2014
From: IMBORNONE, JAMES FRANCIS; WANG, XINWEI; LUO, ZHENYING; ZHANG, XIANGDONG
To: QUALCOMM INCORPORATED
Reel/Frame 032099/0462 →
Continuity (1)
Related Publication 20150042399A1 · Feb 12, 2015