Method of back-end-of-line (BEOL) fabrication, and devices formed by the method
In a method for forming a semiconductor device, an interconnect structure over a semiconductor substrate is provided. The interconnect structure includes a first dielectric layer and a conductive pattern inside a trench in the first dielectric layer. An etch stop layer (ESL) is formed over the interconnect structure. An interface layer comprising elemental silicon is deposited over the ESL. A second dielectric layer is then formed over the interface layer.
1. A method for forming a semiconductor device, comprising steps:
providing an interconnect structure over a semiconductor substrate, the interconnect structure comprising a first dielectric layer and a conductive pattern inside a trench in the first dielectric layer;
forming an etch stop layer (ESL) over the interconnect structure;
depositing an interface layer comprising elemental silicon over the ESL; and
forming a second dielectric layer over the interface layer, wherein the step of forming the second dielectric layer comprises a process using an oxidizing agent, and the interface layer comprising elemental silicon is partially oxidized by the oxidizing agent to become an interface layer comprising silicon-rich oxide having a formula of SiOx, where x is less than 2, or a mixture of elemental silicon (Si) and silicon dioxide (SiO 2 ).
2. The method of claim 1 , wherein the interconnect structure further comprises a pre-etch-stop layer (pre-ESL) over the conductive pattern.
3. The method of claim 2 , wherein the step of providing an interconnect structure over a semiconductor substrate comprises:
forming a first dielectric layer over a semiconductor substrate;
forming a trench in the first dielectric layer, the trench having at least one side wall and a bottom wall;
forming a barrier layer over the bottom wall and along the at least one side wall of the trench;
filling the trench with a conductive pattern; and
forming a pre-ESL over the conductive pattern.
4. The method of claim 3 , wherein the barrier layer is formed by depositing a diffusion barrier material.
5. The method of claim 3 , wherein the conductive pattern comprises copper.
6. The method of claim 3 , wherein the step of forming the pre-ESL layer comprises depositing a material comprising cobalt.
7. The method of claim 2 , wherein the interface layer comprising elemental silicon is deposited over the ESL using a process of plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).
8. The method of claim 2 , wherein the interface layer comprising elemental silicon is a layer of silicon at a thickness in a range from 5 Angstroms to 100 Angstroms.
9. The method of claim 2 , wherein the step of forming a second dielectric layer comprises a curing process using ultra-violet light and an oxidizing gas.
10. The method of claim 2 , wherein both the first dielectric layer and the second dielectric layer comprise a low-k material.
11. A method for forming a semiconductor device, comprising steps:
providing an interconnect structure over a semiconductor substrate, the interconnect structure comprising a first low-k dielectric layer having a trench therein, a conductive pattern filled inside the trench, and a pre-etch-stop layer (pre-ESL) over the conductive pattern;
forming an etch stop layer (ESL) over the interconnect structure;
depositing an interface layer comprising elemental silicon over the ESL; and
forming a second low-k dielectric layer over the interface layer, wherein the step of forming the second low-k dielectric layer comprises a process using an oxidizing agent, and the interface layer comprising elemental silicon is partially oxidized by the oxidizing agent to become an interface layer comprising silicon-rich oxide having a formula of SiOx, where x is less than 2, or a mixture of elemental silicon (Si) and silicon dioxide (SiO 2 ).
12. The method of claim 11 , wherein the step of providing an interconnect structure over a semiconductor substrate comprises:
forming a first low-k dielectric layer over a semiconductor substrate;
etching the first low-k dielectric layer to form a trench in the first low-k dielectric layer, the trench having at least one side wall and a bottom wall;
forming a barrier layer over the bottom wall and along the at least one side wall of the trench;
filling the trench with a conductive pattern comprising copper; and
forming a pre-ESL comprising cobalt over the conductive pattern.
13. The method of claim 11 , further comprising a barrier layer disposed over a bottom wall and along a side wall of the trench.
14. The method of claim 11 , wherein the interface layer comprising elemental silicon is a layer of silicon at a thickness in a range from 5 Angstroms to 100 Angstroms.
15. The method of claim 11 , wherein the step of forming the second low-k dielectric layer comprises a curing process using ultra-violet light and an oxidizing gas.
16. A semiconductor device, comprising
an interconnect structure over a semiconductor substrate, the interconnect structure comprising a first low-k dielectric layer having a trench therein, and a conductive pattern disposed inside the trench;
an etch stop layer (ESL) over the interconnect structure;
an interface layer over the ESL, wherein the interface layer comprises a layer of silicon dioxide (SiO 2 ) and a layer of silicon-rich oxide; and
a second low-k dielectric layer over the interface layer.
17. The device of claim 16 , wherein the interconnect structure further comprises a barrier layer disposed over a bottom wall and along a side wall of the trench in the first low-k dielectric layer, and a pre-etch-stop layer (pre-ESL) over the conductive pattern.
18. The device of claim 16 , wherein the silicon-rich oxide having a formula of SiOx, where x is in a range from 1 to less than 2.
19. The device of claim 16 , wherein the interface layer comprising silicon-rich oxide is different from the first low-k dielectric layer or the second low-k dielectric layer.
20. The device of claim 17 , wherein the conductive pattern comprises copper, and the pre-ESL comprises cobalt.
21. The method of claim 1 , wherein the interface layer comprises more than 50% by weight of elemental silicon.
22. The method of claim 1 , wherein the interface layer comprises more than 75% by weight of elemental silicon.
23. The method of claim 1 , wherein the interface layer consists essentially of elemental silicon.
24. The semiconductor device of claim 16 , wherein the silicon-rich Oxide has a formula of SiO x , where x is less than 2.
25. The semiconductor device of claim 16 , wherein the interface layer comprises a mixture of elemental silicon (Si) and silicon (SiO 2 ).