Controllable polarity FET based arithmetic and differential logic
A logic gate with three inputs A, B, and C, and one output implementing a function MAJ(A,B,C)=A*B+B*C+A*C comprising two mutually exclusive transmission gates (TGs) connected in series, based on two parallel double-gate controllable polarity devices, a polarity of each being controlled by input A and a conduction being controlled by input B, or vice-versa, in opposite polarities, and that route either an input A or C from one side of the transmission gates to the output.
1. A logic gate with three inputs A, B, and C, and one output implementing a function MAJ(A,B,C)=A*B+B*C+A*C comprising
two mutually exclusive transmission gates (TGs) connected in series, based on two parallel double-gate controllable polarity devices, a polarity of each being controlled by input A and a conduction being controlled by input B, or vice-versa, in opposite polarities, and that route either an input A or C from one side of the transmission gates to the output implementing the function MAJ(A,B,C) =A*B+B*C+A*C.
2. The logic gate of claim 1 , wherein the output is a node where the two transmission gates are connected.
3. The logic gate of claim 1 , wherein the two transmission gates are replaced by pass gates (PGs) based on single double-gate controllable polarity devices controlled by inputs A and B.
4. A Full-Adder comprising a XOR-3 gate and the logic gate of claim 1 , wherein the XOR-3 gate is based on further transmission gates (TGs) that route either the input C or an input C′ from one side of the further transmission gates to a further output.
5. The Full-Adder of claim 3 , wherein the further output is a node where the two further transmission gates are connected.
6. The Full-Adder of claim 4 , wherein the two transmission gates are replaced by Pass-Gates (PGs) based on controllable polarity double-gate devices.
7. A vertically stack implementation of Full-Adders described in claim 4 , wherein the double-gate controllable polarity devices for XOR-3 and majority are vertically stacked and sharing the same gate-input signals.
8. A circuit in Differential Cascade Voltage Switch Logic (DCVSL) style, presenting power gating capabilities, comprising:
two mutually exclusive pull-down networks, each consisting of either standard unipolar or double-gate controllable polarity devices;
two n-type transistors driven by a sleep signal, placed in parallel to the pull-down networks; and
two double-gate controllable polarity transistors used as pull-up devices, wherein the first gate is used for the standard differential logic feedback and the second gate is driven by a sleep signal.
9. A cascade implementation of power-gated circuits comprising an alternating use of the circuit according to claim 8 and standard non-power-gated DCVSL style circuits.