Instruction filtering
Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.
1. A system for instruction filtering, the system comprising:
a memory configured to store instructions accessible by a processor; and
the processor comprising a tracking array and a tracked instruction logic block, wherein the processor is configured to perform a method comprising:
detecting, by the processor, a tracked instruction in an instruction stream;
storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction;
accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction;
marking, by the processor, instruction text of the subsequently fetched instruction to indicate that the subsequently fetched instruction is a previously executed tracked instruction based on the indication of the tracked instruction from the tracking array; and
preventing an action of the tracked instruction logic block based on detecting the marked instruction text.
2. The system of claim 1 , wherein accessing of the tracking array is performed in parallel with accessing an instruction cache prior to instruction decoding of the subsequently fetched instruction.
3. The system of claim 1 , wherein the processor is configured to perform:
selecting entries to remove from the tracking array randomly based on detecting tracked instructions; and
removing the randomly selected entries from the tracking array.
4. The system of claim 1 , wherein the tracked instruction is a branch prediction preload instruction, the tracking array is a branch prediction preload tracking array, the tracked instruction logic block is branch prediction logic, and the action is installation of a to be preloaded branch prediction to a branch predictor.
5. The system of claim 4 , wherein the processor is configured to perform:
checking a branch type of the to be preloaded branch prediction identified in the branch prediction preload instruction; and
based on determining that the branch type is a multi-target branch, the prevented action is preventing installation of the to be preloaded branch prediction to a least recently used position of the branch predictor, and instead forcing installation of the to be preloaded branch prediction into a predetermined set of the branch predictor.
6. The system of claim 5 , wherein the branch predictor further comprises a branch target buffer and a branch target buffer preload table, and the processor is configured to perform:
preventing movement of an entry in the branch target buffer preload table to the branch target buffer based on determining that the branch type of the entry is the multi-target branch.
7. The system of claim 6 , wherein the processor is configured to perform:
determining that a branch alias exists at a location in the branch target buffer preload table where a multi-target branch is predicted but does not exist;
storing an indication of the branch alias for the location in the branch target buffer preload table; and
invalidating an entry at the location in the branch target buffer preload table based on detecting the stored indication of the branch alias on a next multi-target branch prediction, and clearing the stored indication of the branch alias.
8. The system of claim 5 , wherein the predetermined set of the branch predictor is determined based on one or more of: a predicted branch instruction address and a thread identifier.