Gate protected semiconductor devices
View Patent ↗Providing gate protection to a group III-semiconductor device by delivering gate overdrive immunity is described herein. The gate protection can be achieved by embedding a gate-voltage-controlling second transistor to the gate electrode of a first transistor. In other words, a first gate electrode of the first semiconductor device is in series with a second source electrode of the second semiconductor device, and a second gate electrode of the second semiconductor device is connected to the second source electrode and the first gate electrode.
1. An integrated group III-nitride device, comprising:
an enhancement-mode high electron mobility transistor (E-HEMT) comprising a first source electrode, a first drain electrode and a first gate electrode; and
a depletion-mode high electron mobility transistor (D-HEMT) comprising a second source electrode, a second drain electrode and a second gate electrode,
wherein the first gate electrode is in series with the second source electrode,
wherein the second gate electrode is connected to the second source electrode and the first gate electrode,
wherein a gate voltage of the E-HEMT is driven by application of an input bias voltage to the second drain electrode, and
wherein a current at the first gate electrode generated in response to the application of the input bias voltage to the second drain electrode is clamped at a saturation current of the D-HEMT.
2. The integrated group III-nitride device of claim 1 , wherein a second size of the D-HEMT structure is smaller than a first size of the E-HEMT structure.
3. The integrated group III-nitride device of claim 1 ,
wherein, in response to the input bias voltage being less than a defined voltage value, the current at the first gate electrode is equal to or less than the saturation current of the D-HEMT structure, and
wherein, in response to the input bias voltage being greater than or equal to the defined voltage value, the current at the first gate electrode is equal to or less than the saturation current of the D-HEMT structure.
4. The integrated group III-nitride device of claim 1 , wherein the first source electrode and the first drain electrode make Ohmic contacts to the E-HEMT structure, the first gate electrode has a Schottky barrier contact to the E-HEMT structure, the second source electrode and the second drain electrode make Ohmic contacts to the D-HEMT structure, and the second gate electrode has a Schottky barrier contact to the D-HEMT structure.
5. The integrated group III-nitride device of claim 1 , wherein the E-HEMT structure comprises a first group III-nitride semiconductor device and the D-HEMT structure comprises a second group III-nitride semiconductor device.
6. A device, comprising:
an enhancement-mode high electron mobility transistor (E-HEMT) comprising a first source electrode, a first drain electrode and a first gate electrode; and
a depletion-mode high electron mobility transistor (D-HEMT) comprising a second source electrode, a second drain electrode and a second gate electrode,
wherein the D-HEMT is connected to the first gate electrode of the E-HEMT in series via connection of the second gate electrode to the second source electrode and the first gate electrode.
7. The device of claim 6 , wherein the second gate electrode comprises a Schottky barrier structure, and wherein the Schottky barrier structure comprises a Schottky barrier contact and a negative charge-trapped region on the second semiconductor substrate.
8. The device of claim 7 , wherein the negative charge-trapped region comprises F ions.
9. The device of claim 6 , wherein the E-HEMT and the D-HEMT are implemented on a same group-III nitride semiconductor material.
10. The device of claim 9 , further comprising an isolation structure that separates the E-HEMT and the D-HEMT.
11. The device of claim 6 , wherein a potential current at the first gate electrode of the E-HEMT generated in response to application of a bias voltage to the second drain electrode of the D-HEMT is clamped based on a saturation current of the D-HEMT.
12. A device, comprising:
an E-HEMT comprising a first source electrode, a first drain electrode and a first gate electrode; and
a D-HEMT comprising a second source electrode, a second drain electrode and a second gate electrode,
wherein the first gate electrode is in series with the second source electrode,
wherein the second gate electrode is connected to the second source electrode and the first gate electrode, and
wherein an overdrive potential of the first gate electrode is controlled based on a saturation current of the D-HEMT when a bias voltage is applied to the second drain electrode.
13. The device of claim 12 , wherein a potential current at the first gate electrode, generated in response to application of a bias voltage to the second drain electrode greater than or equal to a defined bias voltage, is less than or equal to the saturation current of the D-HEMT structure.
14. The device of claim 12 , wherein the second semiconductor structure has a resistance that varies as a function of the bias voltage to facilitate the preventing the first gate electrode of the E-HEMT structure from reaching the overdrive potential.
15. The device of claim 12 , wherein the E-HEMT structure is configured to receive a gate current in response to application of the bias voltage to the second drain electrode and wherein a potential gate voltage of the E-HEMT structure is clamped at a value less than or equal to the defined voltage value based on the saturation current of the D-HEMT structure.
16. The device of claim 15 , wherein the defined voltage value is at least about 2 volts.
17. The device of claim 12 , wherein the E-HEMT structure comprises a first vertical layered heterostructure and the D-HEMT structure comprises a second vertical layered heterostructure, and
wherein the first vertical layered heterostructure and the second vertical layered heterostructure are implemented on a same group-III nitride semiconductor material.