IP Library › Granted Patent US 9,165,337

Granted Patent B2

US 9,165,337 · App. 14/027,816 · Granted Oct 20, 2015

Command instruction management

Inventors: Murat Balci (Orlando, FL); Christopher Paul Frascati (Oviedo, FL); Avinash Seetharamaiah (Chuluota, FL)

Assignee: QUALCOMM Incorporated

G06T1/20 G06F9/3881 G06F9/50 G06T1/60

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Quick Facts

Patent No.: US 9,165,337
App. No.: 14/027,816
Granted: Oct 20, 2015
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

Techniques are described for writing commands to memory units of a chain of memory units of a command buffer. The techniques may write the commands, and if during the writing, it is determined that there is not sufficient space in the chain of memory unit, the techniques may flush previously confirmed commands. If after the writing, the techniques determine that there is not sufficient space in an allocation list for the handles associated with the commands, the techniques may flush previously confirmed commands.

Claims (84)

1. A method for storing commands, the method comprising:

writing, with a processor, a current set of commands to a chain of memory units in a command buffer starting from a current confirm point in a memory unit of the chain of memory units, wherein the chain of memory units stores previously confirmed commands that the processor stored in the chain of memory units before the writing of the current set of commands, and wherein the previously confirmed commands have handles that are stored in an allocation list;

determining, with the processor, at least one of:

whether an end of the chain of memory units is reached with commands of the current set of commands that have not yet been written to the chain of memory units during the writing of the current set of commands; or

whether there is sufficient space in the allocation list to store handles associated with the current set of commands after the writing of the current set of commands; and

submitting for eventual execution, the previously confirmed commands that were stored by the processor in the chain of memory units before the writing of the current set of commands if, based on the determination, the end of the chain of memory units is reached with commands of the current set of commands that have not yet been written to the chain of memory units or if, based on the determination, there is insufficient space in the allocation list to store handles associated with the current set of commands.

2. The method of claim 1 , further comprising:

storing the handles associated with the current set of commands in a temporary list during the writing of the current set of commands,

wherein determining whether there is sufficient space in the allocation list comprises determining whether adding the handles in the temporary list to the allocation list requires more space in the allocation list than available by attempting to add the handles in the temporary list to the allocation list.

3. The method of claim 1 , further comprising:

storing the handles associated with the current set of commands in the allocation list if there is sufficient space in the allocation list to store the handles associated with the current set of commands after writing the current set of commands; and

moving the current confirm point to another memory unit if there is sufficient space in the allocation list to store the handles associated with the current set of commands after writing the current set of commands.

4. The method of claim 1 , further comprising:

releasing memory units from the chain of memory units prior to the memory unit in which the current confirm point is identified; and

allocating one or more additional memory units to the chain of memory units if the end of the chain of memory units is reached with commands of the current set of commands that have not yet been written to the chain of memory units.

5. The method of claim 1 , further comprising:

clearing the allocation list if there is not sufficient space in the allocation list to store the handles associated with the current set of commands.

6. The method of claim 1 , wherein writing the current set of commands in the chain of memory units starting from the current confirm point in the memory unit comprises writing the current set of commands in the chain of memory units without determining whether there is sufficient space in the chain of memory units to store the current set of commands.

7. The method of claim 1 , wherein writing the current set of commands in the chain of memory units starting from the current confirm point in the memory unit comprises writing the current set of commands in the chain of memory units without determining whether there is sufficient space in the allocation list to store the handles associated with the current set of commands.

8. The method of claim 1 , wherein the processor comprises a first processor, and wherein the current set of commands are for execution by a second, different processor.

9. The method of claim 8 , wherein the first processor comprises a central processing unit (CPU) and the second processor comprises a graphics processing unit (GPU).

10. A device comprising:

a system memory comprising a command buffer; and

a processor configured to:

write a current set of commands to a chain of memory units in the command buffer starting from a current confirm point in a memory unit of the chain of memory units, wherein the chain of memory units stores previously confirmed commands that the processor stored in the chain of memory units before the writing of the current set of commands, and wherein the previously confirmed commands have handles that are stored in an allocation list;

determine at least one of:

whether there is sufficient space in the allocation list to store handles associated with the current set of commands after the writing of the current set of commands; and

submit for eventual execution the previously confirmed commands that were stored by the processor in the chain of memory units before the writing of the current set of commands if, based on the determination, the end of the chain of memory units is reached with commands of the current set of commands that have not yet been written to the chain of memory units or if, based on the determination, there is insufficient space in the allocation list to store handles associated with the current set of commands.

11. The device of claim 10 , wherein the processor is configured to:

store the handles associated with the current set of commands in a temporary list during the writing of the current set of commands,

wherein, to determine whether there is sufficient space in the allocation list, the processor is configured to determine whether adding the handles in the temporary list to the allocation list requires more space in the allocation list than available by attempting to add the handles in the temporary list to the allocation list.

12. The device of claim 10 , wherein the processor is configured to:

store the handles associated with the current set of commands in the allocation list if there is sufficient space in the allocation list to store the handles associated with the current set of commands after writing the current set of commands; and

move the current confirm point to another memory unit if there is sufficient space in the allocation list to store the handles associated with the current set of commands after writing the current set of commands.

13. The device of claim 10 , wherein the processor is configured to:

release memory units from the chain of memory units prior to the memory unit in which the current confirm point is identified; and

allocate one or more additional memory units to the chain of memory units if the end of the chain of memory units is reached with commands of the current set of commands that have not yet been written to the chain of memory units.

14. The device of claim 10 , wherein the processor is configured to:

clear the allocation list if there is not sufficient space in the allocation list to store the handles associated with the current set of commands.

15. The device of claim 10 , wherein the processor is configured to write the current set of commands in the chain of memory units without determining whether there is sufficient space in the chain of memory units to store the current set of commands.

16. The device of claim 10 , wherein the processor is configured to write the current set of commands in the chain of memory units without determining whether there is sufficient space in the allocation list to store the handles associated with the current set of commands.

17. The device of claim 10 , wherein the processor comprises a first processor, the device further comprising a second, different processor, and wherein the current set of commands are for execution by the second processor.

18. The device of 17 , wherein the first processor comprises a central processing unit (CPU) and the second processor comprises a graphics processing unit (GPU).

19. A non-transitory computer-readable storage medium having instructions stored thereon that when executed cause one or more processors to:

write a current set of commands to a chain of memory units in a command buffer starting from a current confirm point in a memory unit of the chain of memory units, wherein the chain of memory units stores previously confirmed commands that the one or more processors stored in the chain of memory unit before the writing of the current set of commands, and wherein the previously confirmed commands have handles that are stored in an allocation list;

determine at least one of:

whether there is sufficient space in an allocation list to store handles associated with the current set of commands after the writing of the current set of commands; and

submit for eventual execution the previously confirmed commands that were stored by the one or more processors in the chain of memory units before the writing of the current set of commands if, based on the determination, the end of the chain of memory units is reached with commands of the current set of commands that have not yet been written to the chain of memory units or if, based on the determination, there is insufficient space in the allocation list to store handles associated with the current set of commands.

20. The computer-readable storage medium of claim 19 , further comprising instructions that cause the one or more processors to:

store the handles associated with the current set of commands in a temporary list during the writing of the current set of commands,

wherein the instructions that cause the one or more processors to determine whether there is sufficient space in the allocation list comprise instructions that cause the one or more processors to determine whether adding the handles in the temporary list to the allocation list requires more space in the allocation list than available by attempting to add the handles in the temporary list to the allocation list.

21. The computer-readable storage medium of claim 19 , further comprising instructions that cause the one or more processors to:

22. The computer-readable storage medium of claim 19 , further comprising instructions that cause the one or more processors to:

release memory units from the chain of memory units prior to the memory unit in which the current confirm point is identified; and

23. The computer-readable storage medium of claim 19 , further comprising instructions that cause the one or more processors to:

clear the allocation list if there is not sufficient space in the allocation list to store the handles associated with the current set of commands.

24. The computer-readable storage medium of claim 19 , wherein the instructions that cause the one or more processors to write the current set of commands in the chain of memory units starting from the current confirm point in the memory unit comprise instructions that cause the one or more processors to write the current set of commands in the chain of memory units without determining whether there is sufficient space in the chain of memory units to store the current set of commands.

25. The computer-readable storage medium of claim 19 , wherein the instructions that cause the one or more processors to write the current set of commands in the chain of memory units starting from the current confirm point in the memory unit comprise instructions that cause the one or more processors to write the current set of commands in the chain of memory units without determining whether there is sufficient space in the allocation list to store the handles associated with the current set of commands.

26. A device comprising:

a system memory comprising a command buffer; and

a processor comprising:

means for writing a current set of commands to a chain of memory units in the command buffer starting from a current confirm point in a memory unit of the chain of memory units, wherein the chain of memory units stores previously confirmed commands that the processor stored in the chain of memory units before the writing of the current set of commands, and wherein the previously confirmed commands have handles that are stored in an allocation list;

means for determining at least one of:

whether there is sufficient space in the allocation list to store handles associated with the current set of commands after the writing of the current set of commands; and

means for submitting for eventual execution the previously confirmed commands that were stored by the processor in the chain of memory units before the writing of the current set of commands if the end of the chain of memory units is reached with commands of the current set of commands that have not yet been written to the chain of memory units or if there is insufficient space in the allocation list to store handles associated with the current set of commands.

27. The device of claim 26 , further comprising:

means for storing the handles associated with the current set of commands in a temporary list during the writing of the current set of commands,

wherein the means for determining whether there is sufficient space in the allocation list comprises means for determining whether adding the handles in the temporary list to the allocation list requires more space in the allocation list than available by attempting to add the handles in the temporary list to the allocation list.

28. The device of claim 26 , further comprising:

means for storing the handles associated with the current set of commands in the allocation list if there is sufficient space in the allocation list to store the handles associated with the current set of commands after writing the current set of commands; and

means for moving the current confirm point to another memory unit if there is sufficient space in the allocation list to store the handles associated with the current set of commands after writing the current set of commands.

29. The device of claim 26 , further comprising:

means for releasing memory units from the chain of memory units prior to the memory unit in which the current confirm point is identified; and

means for allocating one or more additional memory units to the chain of memory units if the end of the chain of memory units is reached with commands of the current set of commands that have not yet been written to the chain of memory units.

30. The device of claim 26 , further comprising:

means for clearing the allocation list if there is not sufficient space in the allocation list to store the handles associated with the current set of commands.

31. The device of claim 26 , wherein the means for writing the current set of commands in the chain of memory units starting from the current confirm point in the memory unit comprises means for writing the current set of commands in the chain of memory units without determining whether there is sufficient space in the chain of memory units to store the current set of commands.

32. The device of claim 26 , wherein the means for writing the current set of commands in the chain of memory units starting from the current confirm point in the memory unit comprises means for writing the current set of commands in the chain of memory units without determining whether there is sufficient space in the allocation list to store the handles associated with the current set of commands.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 16, 2013

From: BALCI, MURAT; FRASCATI, CHRISTOPHER PAUL; SEETHARAMAIAH, AVINASH

To: QUALCOMM INCORPORATED

Reel/Frame 031213/0371 →

Continuity (2)

Provisional Application 61829487 · May 31, 2013

Related Publication 20140354660A1 · Dec 4, 2014