Manufacturing method of semiconductor device
Even when a semiconductor device having field effect transistors driven by relatively different power supply voltages provided over a semiconductor substrate is manufactured by the gate-last process, the breakdown voltage of the transistor on the higher voltage side can be ensured. When forming, over the substrate by the gate-last process, a MOSFET of a core region driven by a first power supply voltage and a MOSFET of a high-voltage region driven by a second power supply voltage higher than the first power supply voltage, the thickness of the hard mask film formed over a dummy gate film of the high-voltage region is made thicker than that of the hard mask film formed over a dummy gate film of the core region, prior to a process of patterning a dummy gate of the MOSFET of the core region and the MOSFET of the high-voltage region. Thereby, the breakdown voltage of MOSFET of the high-voltage region can be ensured.
1. A manufacturing method of a semiconductor device comprising the steps of:
(a) forming a first insulating film over a semiconductor substrate having a formation region of a first field effect transistor driven by a first power supply voltage, and a formation region of a second field effect transistor driven by a second power supply voltage higher than the first power supply voltage;
(b) depositing a dummy gate film over the first insulating film;
(c) depositing a hard mask film over the dummy gate film;
(d) processing the hard mask film so that thickness of the hard mask film of the formation region of the second field effect transistor becomes thicker than the thickness of the hard mask film of the formation region of the first field effect transistor;
(e) patterning the dummy gate film and the hard mask film after the step (d);
(f) after the step (e), forming a semiconductor region for the source and drain of the first field effect transistor;
(g) after the step (e), forming a semiconductor region for the source and drain of the second field effect transistor;
(h) after the step (f) and step (g), performing heat treatment to activate the semiconductor regions for the source and drain of the first field effect transistor and the second field effect transistor;
(i) after the step (h), depositing a second insulating film over the semiconductor substrate and thereafter removing the second insulating film until the dummy gate film is exposed;
(j) after the step (i), removing the dummy gate film exposed from the second insulating film;
(k) after the step (j), forming a third insulating film having a dielectric constant higher than the first insulating film in the removal region of the dummy gate film; and
(l) after the step (k), forming a gate electrode formed of a conductor film containing metal as a main component via the third insulating film in the removal region of the dummy gate film.
2. The manufacturing method of a semiconductor device according to claim 1 ,
wherein the step (f) includes the steps of:
forming a semiconductor region having a relatively low impurity concentration for the source and drain of the first field effect transistor; and
forming a semiconductor region having a relatively high impurity concentration for the source and drain of the first field effect transistor, and
wherein the step (g) includes the steps of:
forming a semiconductor region having a relatively low impurity concentration for the source and drain of the second field effect transistor; and
forming a semiconductor region having a relatively high impurity concentration for the source and drain of the second field effect transistor.
3. The manufacturing method of a semiconductor device according to claim 2 , wherein
the depth of the low impurity concentration semiconductor region of the second field effect transistor is deeper than the depth of the low impurity concentration semiconductor region of the first field effect transistor, and
the depth of the high impurity concentration semiconductor region of the second field effect transistor is deeper than the depth of the high impurity concentration semiconductor region of the first field effect transistor.
4. The manufacturing method of a semiconductor device according to claim 1 ,
wherein the semiconductor substrate has a memory region having disposed therein a nonvolatile memory cell in which a control gate and a memory gate are arranged in alignment along the upper surface of the semiconductor substrate via a memory insulating film, and
wherein the method comprises a step of, after the step (b) and prior to the step (c), processing the dummy gate film of the memory region so that the thickness of the dummy gate film of the memory region becomes thinner than the thickness of the dummy gate film of the formation region of the first field effect transistor and the formation region of the second field effect transistor.
5. The manufacturing method of a semiconductor device according to claim 4 ,
wherein the dummy gate film is formed of polycrystalline silicon, and
wherein the method comprises a step of forming the control gate by the dummy gate film.
6. The manufacturing method of a semiconductor device according to claim 4 , comprising a step of
processing the memory gate so that the height of the upper surface of the memory gate becomes the height of the upper surface of the hard mask film over the upper surface of the control gate formed by the dummy gate film.
7. The manufacturing method of a semiconductor device according to claim 6 , comprising a step of
forming a silicide layer on the upper part of the memory gate.
8. The manufacturing method of a semiconductor device according to claim 1 ,
wherein the semiconductor substrate has a memory region having disposed therein a nonvolatile memory cell in which a control gate and a memory gate are arranged in alignment along the upper surface of the semiconductor substrate via a memory insulating film, and
wherein the method comprises the steps of:
in the step (i), removing the second insulating film until the dummy gate film of the memory region, the formation region of the first field effect transistor, and the formation region of the second field effect transistor are exposed;
in the step (j), removing the dummy gate film of the memory region, the formation region of the first field effect transistor, and the formation region of the second field effect transistor;
in the step (k), forming the third insulating film in the removal region of the dummy gate film of the memory region, the formation region of the first field effect transistor, and the formation region of the second field effect transistor; and
in the step (l), depositing the conductor film over the semiconductor substrate so as to be buried in the removal region of the dummy gate film of the memory region, the formation region of the first field effect transistor, and the formation region of the second field effect transistor, thereafter, by removing the upper part of the conductor film, forming a control gate formed of the conductor film via the third insulating film in the removal region of the dummy gate film of the memory region, and forming a gate electrode formed of the conductor film via the third insulating film in the removal region of the dummy gate film of the formation region of the first field effect transistor and the formation region of the second field effect transistor.