Nonvolatile semiconductor memory device and method of manufacturing the same

1. A nonvolatile semiconductor memory device comprising:

a structure including first to n-th semiconductor layers (n is a natural number equal to or larger than 2) stacked in a first direction, and an upper insulating layer stacked on the n-th semiconductor layer in the first direction, the structure extending in a second direction crossing to the first direction; and

first to n-th NAND strings provided on surfaces of the first to n-th semiconductor layers in a third direction crossing to the first and second directions,

wherein each of the first to n-th NAND strings includes memory cells connected in series,

each of the memory cells includes a charge storage layer and a control gate electrode, and

the upper insulating layer is not provided on the surface of the first to n-th semiconductor layers in the third direction and includes an oxide or a nitride of an element selected from a group of Al, Hf, Ta, Ti, and W.

2. The device of claim 1 , wherein the upper insulating layer which is covered with the control gate electrode has a width equal to or narrower than a width of the n-th semiconductor layer in the third direction.

3. The device of claim 1 , wherein the upper insulating layer which is covered with the control gate electrode has a corner portion in a cross section perpendicular to the second direction, and the upper insulating layer which is not covered with the control gate electrode has a round portion in the cross section.

4. The device of claim 1 , wherein the charge storage layer comprises conductive layers stacked in the third direction and an insulating layer between the conductive layers.

5. The device of claim 1 , wherein each of the memory cells includes a first insulating layer, the charge storage layer, a second insulating layer, and the control gate electrode in the order stated on a surface of the first to n-th semiconductor layers in the third direction.

6. The device of claim 1 , wherein the structure includes a slit passing through the upper insulating layer and the first to n-th semiconductor layers in the first direction, a first insulating layer covering a surface of the first to n-th semiconductor layers provided in the slit in the third direction, a conductive layer provided in the slit, and a second insulating layer covering the conductive layer in the first direction.

7. The device of claim 1 , wherein each of the memory cells includes a first insulating layer and the charge storage layer in the order stated on a surface of the first to n-th semiconductor layers in the third direction, and includes a second insulating layer and the control gate electrode covering two surfaces of the charge storage layer in the second direction.

8. The device of claim 1 , wherein the structure includes first to (n+1)-th insulating layers stacked in the first direction,

the i-th semiconductor layer (i is one of 1 to n) is provided between the i-th insulating layer and the (i+1)-th insulating layer,

each of the first to n-th semiconductor layers has a width narrower than that of each of the first to (n+1)-th insulating layers in the third direction, and

the charge storage layers of the memory cells are provided in concave portions between the first to (n+1)-th insulating layers respectively.

9. The device of claim 1 , wherein the structure includes first to (n+1)-th insulating layers stacked in the first direction,

the i-th semiconductor layer (i is one of 1 to n) is provided between the i-th insulating layer and the (i+1)-th insulating layer, and

the upper insulating layer which is covered with the control gate electrode has a width equal to or narrower than that of the (n+1)-th insulating layer in the third direction.

10. The device of claim 9 , wherein each of the first to n-th semiconductor layers has a width wider than a width of each of the first to (n+1)-th insulating layers in the third direction, and

the charge storage layers of the memory cells are provided along convex portions of the first to n-th semiconductor layers respectively.

11. The device of claim 1 , wherein the charge storage layers of the memory cells are separated from one another.

12. A nonvolatile semiconductor memory device comprising:

a structure including first to n-th semiconductor layers (n is a natural number equal to or larger than 2) stacked in a first direction, and an upper insulating layer stacked on the n-th semiconductor layer in the first direction, the structure extending in a second direction crossing to the first direction; and

first to n-th memory cells provided on surfaces of the first to n-th semiconductor layers in a third direction crossing to the first and second directions,

wherein each of the first to n-th memory cells includes a charge storage layer and a control gate electrode, and

the upper insulating layer is not provided on the surfaces of the first to n-th semiconductor layers in the third direction and includes an oxide or a nitride of an element selected from a group of Al, Hf, Ta, Ti, and W.

13. The device of claim 12 , wherein the upper insulating layer which is covered with the control gate electrode has a width equal to or narrower than a width of the n-th semiconductor layer in the third direction.

14. The device of claim 12 , wherein the upper insulating layer which is covered with the control gate electrode has a corner portion in a cross section perpendicular to the second direction, and the upper insulating layer which is not covered with the control gate electrode has a round portion in the cross section.

15. The device of claim 12 , wherein the charge storage layer comprises conductive layers stacked in the third direction and an insulating layer between the conductive layers.

16. The device of claim 12 , wherein each of the memory cells includes a first insulating layer, the charge storage layer, a second insulating layer, and the control gate electrode in the order stated on a surface of the first to n-th semiconductor layers in the third direction.

17. The device of claim 12 , wherein the structure includes a slit passing through the upper insulating layer and the first to n-th semiconductor layers in the first direction, a first insulating layer covering a surface of the first to n-th semiconductor layers provided in the slit in the third direction, a conductive layer provided in the slit, and a second insulating layer covering the conductive layer in the first direction.

18. The device of claim 12 , wherein each of the memory cells includes a first insulating layer and the charge storage layer in the order stated on a surface of the first to n-th semiconductor layers in the third direction, and includes a second insulating layer and the control gate electrode covering two surfaces of the charge storage layer in the second direction.

19. The device of claim 12 , wherein the structure includes first to (n+1)-th insulating layers stacked in the first direction,

the i-th semiconductor layer (i is one of 1 to n) is provided between the i-th insulating layer and the (i+1)-th insulating layer,

each of the first to n-th semiconductor layers has a width narrower than that of each of the first to (n+1)-th insulating layers in the third direction, and

the charge storage layers of the memory cells are provided in concave portions between the first to (n+1)-th insulating layers respectively.

20. The device of claim 12 , wherein the structure includes first to (n+1)-th insulating layers stacked in the first direction,

the i-th semiconductor layer (i is one of 1 to n) is provided between the i-th insulating layer and the (i+1)-th insulating layer, and

the upper insulating layer which is covered with the control gate electrode has a width equal to or narrower than that of the (n+1)-th insulating layer in the third direction.

21. The device of claim 20 , wherein each of the first to n-th semiconductor layers has a width wider than a width of each of the first to (n+1)-th insulating layers in the third direction, and

the charge storage layers of the memory cells are provided along convex portions of the first to n-th semiconductor layers respectively.

22. The device of claim 12 , wherein the charge storage layers of the memory cells are separated from one another.