Reversed stack MTJ

1. An integrated circuit device, comprising:

a substrate;

a magnetic tunneling junction (MTJ) formed over a surface of the substrate, the MTJ comprising;

a free layer configured to switch between at least two different magnetic orientations, arranged over the surface of the substrate;

an insulating barrier layer arranged over the free layer; and

a pinned layer having a fixed magnetic orientation, arranged over the insulating barrier layer, wherein the free layer is connected to a bottom electrode and the pinned layer is connected to a top electrode, and wherein the top electrode, the pinned layer and the insulating barrier layer constitute a stack having substantially aligned vertical sidewalls.

2. The integrated circuit device of claim 1 , further comprising a first set of sidewall spacers, arranged over an upper surface of the free layer and abutting outer sidewalls of the stack.

3. The integrated circuit device of claim 1 , wherein the free layer is wider than the pinned layer.

4. The integrated circuit device of claim 1 , wherein:

the free layer comprises a central region and a perimeter region;

the pinned layer is co-extensive with the central region; and

the pinned layer does not extend over the perimeter region.

5. The integrated circuit device of claim 2 , further comprising a second set of sidewall spacers that is formed above the perimeter region and to the sides of the first set of sidewall spacers.

6. The integrated circuit device of claim 4 , wherein the free layer has etch process induced defects in the perimeter region but not within the central region.

7. The integrated circuit device of claim 4 , wherein a portion of the free layer that is located within the perimeter region and does not extend to the central region is in a non-ferromagnetic state.

8. The integrated circuit device of claim 1 , wherein:

the substrate is a semiconductor substrate; and

the magnetic tunneling junction is a memory cell in a magnetoresitive random access memory array.

9. The integrated circuit device of claim 8 , further comprising:

bit lines positioned between the memory array and the substrate; and

word lines running at cross-angles with the bit lines and located above the memory array.

10. The integrated circuit device of claim 9 , further comprising:

transistors formed at the surface of the semiconductor substrate;

wherein there is one of the transistors for each memory cell in the memory array;

the transistors are coupled to electrodes of the memory cells; and

the electrodes to which the transistors are coupled are on the free layer-sides of the memory cells.

11. An integrated circuit (IC) comprising:

a semiconductor substrate;

a bottom electrode disposed over the semiconductor substrate;

a first ferromagnetic layer disposed over the bottom electrode and configured to switch between at least two different magnetic orientations, wherein the first ferromagnetic layer abuts a top surface of the bottom electrode and has a footprint smaller than a footprint of the bottom electrode;

an insulating barrier layer disposed over the first ferromagnetic layer;

a second ferromagnetic layer disposed over the insulating barrier layer and having a fixed magnetic orientation;

an anti-ferromagnetic layer disposed over the second ferromagnetic layer; and

a top electrode disposed over the anti-ferromagnetic layer.

12. The IC of claim 11 , wherein the insulating barrier layer, the second ferromagnetic layer, the anti-ferromagnetic layer and the top electrode together form a substantially aligned vertical stack, and wherein the vertical stack has a smaller footprint than the footprint of the first ferromagnetic layer.

13. The IC of claim 12 , further comprising:

a first set of sidewall spacers disposed over the first ferromagnetic layer, on opposing sides of the vertical stack; and

a second set of sidewall spacers disposed over the bottom electrode on outer sides of the first set of sidewall spacers.

14. The IC of claim 13 , further comprising:

an interlayer disposed over the second ferromagnetic layer; and

a third ferromagnetic layer disposed between the interlayer and the anti-ferromagnetic layer.

15. The IC of claim 14 , wherein:

the bottom electrode and the top electrode comprise Ta (tantalum);

the first, second and third ferromagnetic layers comprise NiFe (nickel iron alloy), CoFe (cobalt iron alloy) or CoFeB (cobalt iron boron alloy);

the interlayer comprises Ru (ruthenium);

the insulating barrier layer comprises MgO (magnesium oxide) or Al 2 O 3 (aluminum oxide);

the anti-ferromagnetic layer comprises PtMn (platinum manganese alloy) or IrMn (iridium manganese alloy); and

the first and second set of sidewall spacers comprise SiN (silicon nitride), SiO x (silicon oxide), or SiON (silicon oxy nitride).

16. An integrated circuit (IC) comprising:

a semiconductor substrate;

a bottom electrode disposed over the semiconductor substrate;

a free layer disposed over the bottom electrode and configured to switch between at least two different magnetic orientations, wherein the free layer comprises non-conductive outer regions separated horizontally by a conductive inner region and wherein, vertical sidewalls of the outer regions of the free layer substantially align with vertical sidewalls of the bottom electrode;

an insulating barrier layer disposed over the free layer;

a pinned layer disposed over the insulating barrier layer and having a fixed magnetic orientation;

an anti-ferromagnetic layer disposed over the pinned layer; and

a top electrode disposed over the anti-ferromagnetic layer.

17. The IC of claim 16 , wherein the outer regions of the free layer are oxidized and non-conductive with respect to their ferromagnetic properties.

18. The IC of claim 16 , wherein the insulating barrier layer, the pinned layer, the anti-ferromagnetic layer and the top electrode together form a substantially aligned vertical stack which resides over the conductive inner region of the free layer.

19. The IC of claim 18 , wherein the vertical stack is laterally offset from a metal line, but coupled to the metal line through the bottom electrode which extends laterally over the metal line.

20. The IC of claim 19 , wherein a portion of the free layer that is disposed above the extended portion of the bottom electrode is non-conductive.