Semiconductor memory device performing pre-read and main read, memory system including the same and method of operating the same
A method of operating a semiconductor memory device includes performing a pre-read and a first main read to selected memory cells in response to a read request, and performing a second main read to the selected memory cells in response to a re-read request.
1. A method of operating a semiconductor memory device, the method comprising:
performing a first pre-read and a first main read based on the first pre-read to selected memory cells in response to a read request, data read by the first pre-read being stored as cache data;
receiving a re-read request; and
in response to the re-read request, performing a second main read to the selected memory cells using the cache data from the first pre-read, thereby omitting a second pre-read to the selected memory cells.
2. The method of claim 1 , wherein the cache data is stored in latches.
3. The method of claim 1 , wherein the performing of the first pre-read and the first main read includes:
storing data read by the first pre-read in first latches; and
performing the first main read through bit lines, on the basis of the data stored in the first latches.
4. The method of claim 3 , wherein the performing of the first pre-read and the first main read further includes copying the data stored in the first latches in second latches before the first main read is performed,
and wherein the data stored in the second latches is the cache data.
5. The method of claim 4 , wherein the performing of the second main read includes:
transmitting the cache data from the second latches to the first latches; and
performing the second main read through the bit lines, on the basis of the cache data stored in the first latches.
6. The method of claim 1 , wherein the re-read request is provided when the number of error bit in data read by the first pre-read and the first main read is higher than a specified value.
7. A method of operating a memory system including memory cells defined as a multi level cell, the method comprising:
performing a first pre-read and a first main read based on the first pre-read when a first read voltage is supplied to a word line of selected memory cells, data read by the first pre-read being stored as first cache data;
performing a second pre-read and a second main read based on the second pre-read when a second read voltage is supplied to the word line, data read by the second pre-read being stored as second cache data;
adjusting the first read voltage and the second read voltage;
performing a third main read based on the first cache data when the adjusted first read voltage is supplied to the word line; and
performing a fourth main read based on the second cache data when the adjusted second read voltage is supplied to the word line.
8. The method of claim 7 , wherein a pre-read to the selected memory cell is omitted in the performing of the third main read and the performing of the fourth main read.
9. The method of claim 7 , wherein the performing of the first pre-read and the first main read includes:
storing data read by the first pre-read through bit lines in first latches;
copying the data stored in the first latches in second latches; and
performing the first main read through the bit lines, on the basis of the data stored in the first latches,
and wherein data stored in the second latches is the first cache data.
10. The method of claim 9 , wherein the performing of the second pre-read and the second main read includes:
storing data read by the second pre-read through the bit lines in the first latches;
copying the data stored in the first latches in third latches; and
performing the second main read through the bit lines, on the basis of the data stored in the first latches,
and wherein data stored in the third latches is the second cache data.
11. The method of claim 10 , wherein the performing of the third main read includes:
transmitting the first cache data from the second latches to the first latches; and
performing the third main read through the bit lines, on the basis of the first cache data stored in the first latches.
12. The method of claim 10 , wherein the performing of the fourth main read includes:
transmitting the second cache data from the third latches to the first latches; and
performing the fourth main read through the bit lines, on the basis of the second cache data stored in the first latches.
13. The method of claim 7 , wherein data stored in the selected memory cells is determined according to result of the first main read and result of the second main read, and the first read voltage and the second read voltage are adjusted when the number of error bit in the detected data is higher than specified value.
14. The method of claim 13 , wherein the third main read and the fourth main read are performed in response to a re-read request, and the re-read request is generated when the number of error bit in the detected data is greater than the specified value.
15. A memory system comprising:
a semiconductor memory device including memory cells and a read and write circuit coupled to the memory cells through bit lines; and
a controller configured to control the semiconductor memory device,
wherein the semiconductor memory device is configured to perform a first pre-read and a first main read based on the first pre-read to the selected memory cells in response to a read request from the controller, and data read by the first pre-read is stored as first cache data in the read and write circuit,
wherein the semiconductor memory device is further configured to perform a second pre-read and a second main read based on the second pre-read to the selected memory cells in response to the read request, and data read by the second pre-read is stored as second cache data in the read and write circuit, and
wherein a first read voltage is applied to a word line coupled to the selected memory cells when the first pre-read and the first main read are performed, and a second read voltage higher than the first read voltage is applied to the word line when the second pre-read and the second main read are performed.
16. The memory system of claim 15 , wherein the controller transmits a re-read request to the semiconductor memory device, and the semiconductor memory device is configured to perform a third main read to the selected memory cells based on the first cache data and a fourth main read to the selected memory cells based on the second cache data in response to the re-read request.
17. The memory system of claim 15 , wherein the controller is configured to control the semiconductor memory device to adjust the first and the second read voltages according to a result of the first and second main reads and to transmit a re-read request to the semiconductor memory device, and
wherein the semiconductor memory device is configured to perform a third main read based on the first cache data when the adjusted first read voltage is applied to the word line, and to perform a fourth main read based on the second cache data when the adjusted second read voltage is applied to the word line.
18. The memory system of claim 15 , wherein the read and write circuit includes page buffers coupled to the bit lines, respectively, and the page buffers include first latches and second latches, and
wherein data read by the first pre-read is stored in the first latches, the first main read is performed based on the data stored in the first latches, and the data stored in the first latches is copied as the first cache data in the second latches before the first main read is performed.
19. The memory system of claim 18 , wherein the first cache data is transmitted from the second latches to the first latches when the re-read request is received, and the second main read is performed based on the cache data stored in the first latches.