Superlattice crenelated gate field effect transistor

1. A field effect transistor device comprising:

a base structure;

a first heterostructure having a first layer located over said base structure, a second layer located over said first layer, and a first 2DxG channel located near the interface between said first and said second layers;

a first delta doping material located in the second layer near the interface between the first layer and second layer;

a second heterostructure having a third layer located in direct contact with said second layer, a fourth layer located over said third layer, and a second 2DxG channel located near the interface between said third and said fourth layers;

a second delta doping material located in the fourth layer near the interface between the third layer and fourth layer;

a third heterostructure having a fifth layer located over said fourth layer, a sixth layer located over said fifth layer, and a third 2DxG channel located near the interface between said fifth and said sixth layers;

a source electrode located over said sixth layer and ohmically connected to each of said 2DxG channels;

a drain electrode located over said sixth layer and ohmically connected to each of said 2DxG channels;

a plurality of trenches located between said source electrode and said drain electrode, each of said trenches having a length, a width and a depth defining a first sidewall surface, a second sidewall surface and a bottom surface located therebetween, the bottom surface of each of said trenches being at or below the first 2DxG channel;

wherein all of said 2DxG channels are either 2DEG channels or 2DHG channels, thereby creating a unipolar device; and

a crenelated gate electrode located over said sixth layer, said gate electrode located within each of said trenches, said gate electrode having a top and a bottom surface, the bottom surface of said gate electrode being in juxtaposition with the first sidewall surface, the bottom surface and the second sidewall surface of each of said trenches.

2. The field effect transistor device of claim 1 , wherein:

said source electrode has a first length edge, a second length edge, a front width edge and a back width edge;

said drain electrode has a first length edge, a second length edge, a front width edge and a back width edge; and

each of said 2DxG channels arc bounded within a quadrilateral defined by the first length edge of said source electrode, the first length edge of said drain electrode, the back width edge of said drain electrode, the second length edge of said drain electrode, the second length edge of said source electrode, and the back width edge of said source electrode.

3. The field effect transistor device of claim 1 , wherein said source electrode has a width and a length, said device further comprising:

a via located under said source electrode, said via having a width and a depth, the width of said via being less than or substantially equal to the width of said source electrode, and the depth of said via being at or below said first 2DxG channel; and

a material located within said via, the material having a dopant to allow low-resistance, ohmic contact between said source electrode and each of said 2DxG channels.

4. The field effect transistor device of claim 1 , wherein said drain electrode has a width and a length, said device further comprising:

a via located under said drain electrode, said via having a width and a depth, the width of said via being less than or substantially equal to the width of said drain electrode, and the depth of said via being at or below said first 2DxG channel; and

a material located within said via, the material having a dopant to allow low-resistance, ohmic contact between said drain electrode and each of said 2DxG channels.

5. The field effect transistor device of claim 1 , wherein, within each of said trenches, the angle between the bottom surface and the first sidewall surface is less than about 110 degrees.

6. The field effect transistor device of claim 1 , wherein:

said source electrode has a first length edge, a second length edge, a front width edge and a back width edge;

said drain electrode has a first length edge, a second length edge, a front width edge and a back width edge; and

the length of each of said trenches is less than or substantially equal to the distance between the front edge of said source electrode and the front edge of said drain electrode.

7. The field effect transistor device of claim 1 , wherein said crenelated gate electrode has a width and a length, and wherein the length of said crenelated gate electrode is less than or substantially equal to the length of each of said trenches.

8. The field effect transistor device of claim 1 , wherein said crenelated gate electrode has a width and a length, and wherein the length of said crenelated gate electrode is greater than the length of each of said trenches.

9. The field effect transistor device of claim 1 , said device further comprising a seventh layer having a dielectric material, said seventh layer located on at least a portion of said sixth layer.

10. A device comprising:

an epitaxial structure comprising a superlattice structure having an uppermost 2DxG channel, a lowermost 2DxG channel induced by the presence of a first delta doping layer, and at least one intermediate 2DxG channel induced by the presence of a second delta doping layer located between said uppermost and said lowermost 2DxG channels;

a source electrode located over said uppermost 2DxG channel and ohmically connected to each of said 2DxG channels;

a drain electrode located over said uppermost 2DxG channel and ohmically connected to each of said 2DxG channels;

a plurality of trenches located between said source electrode and said drain electrode, each of said trenches having a length, a width and a depth defining a first sidewall surface, a second sidewall surface and a bottom surface located therebetween, the bottom surface of each of said trenches being at or below the lowermost 2DxG channel;

wherein all of said 2DxG channels are either 2DEG channels or 2DHG channels, thereby creating a unipolar device; and

a crenelated gate electrode located over said uppermost 2DxG channel, said gate electrode located within each of said trenches, said gate electrode having a top and a bottom surface, the bottom surface of said gate electrode being in juxtaposition with the first sidewall surface, the bottom surface and the second sidewall surface of each of said trenches.

11. The device of claim 10 , wherein said superlattice structure comprises a plurality of heterostructures, each of said heterostructures having a first layer, and a second layer located over said first layer, wherein one of said 2DxG channels is located near the interface between said first layer and said second layer.

12. The device of claim 10 , wherein:

said source electrode has a first length edge, a second length edge, a front width edge and a back width edge;

said drain electrode has a first length edge, a second length edge, a front width edge and a back width edge; and

each of said 2DxG channels are bounded within a quadrilateral defined by the first length edge of said source electrode, the first length edge of said drain electrode, the back width edge of said drain electrode, the second length edge of said drain electrode, the second length edge of said source electrode, and the back width edge of said source electrode.

13. The device of claim 10 , wherein said source electrode has a width and a length, said device further comprising:

a via located under said source electrode, said via having a width and a depth, the width of said via being less than or substantially equal to the width of said source electrode, and the depth of said via being at or below said lowermost 2DxG channel; and

a material located within said via, the material having a dopant to allow low-resistance, ohmic contact between said source electrode and each of said 2DxG channels.

14. The device of claim 10 , wherein said drain electrode has a width and a length, said device further comprising:

a via located under said drain electrode, said via having a width and a depth, the width of said via being less than or substantially equal to the width of said drain electrode, and the depth of said via being at or below said lowermost 2DxG channel; and

a material located within said via, the material having a dopant to allow low-resistance, ohmic contact between said drain electrode and each of said 2DxG channels.

15. The device of claim 10 , wherein, within each of said trenches, the angle between the bottom surface and the first sidewall surface is less than about 110 degrees.

16. The device of claim 10 , wherein:

said source electrode has a first length edge, a second length edge, a front width edge and a back width edge;

said drain electrode has a first length edge, a second length edge, a front width edge and a back width edge; and

the length of each of said trenches is less than or substantially equal to the distance between the front edge of said source electrode and the front edge of said drain electrode.

17. The device of claim 10 , wherein said crenelated gate electrode has a width and a length, and wherein the length of said crenelated gate electrode is less than or substantially equal to the length of each of said trenches.

18. The device of claim 10 , wherein said crenelated gate electrode has a width and a length, and wherein the length of said crenelated gate electrode is greater than the length of each of said trenches.

19. The device of claim 10 , said device further comprising a layer having a dielectric material, said layer located on at least a portion of said superlattice structure.

20. A device comprising:

an epitaxial structure comprising a superlattice structure having an upper 2DxG channel and a lower 2DxG channel, said lower 2DxG channel induced by the presence of a first delta doping layer;

a source electrode having a first length edge, a second length edge, a front width edge and a back width edge, said source electrode located over said upper 2DxG channel and ohmically connected to each of said 2DxG channels;

a drain electrode having a first length edge, a second length edge, a front width edge and a back width edge, said drain electrode located over said upper 2DxG channel and ohmically connected to each of said 2DxG channels;

a first current-flow boundary positioned between the first length edge of said source electrode and the first length edge of said drain electrode;

a second current-flow boundary positioned between the second length edge of said source electrode and the second length edge of said drain electrode, wherein said first current-flow boundary and said second current-flow boundary substantially preclude current flow between said source electrode and said drain electrode outside of the area defined by said first current-flow boundary and said second current-flow boundary;

at least one trench located between said source electrode and said drain electrode, said trench having a length, a width and a depth defining a first sidewall surface, a second sidewall surface and a bottom surface located therebetween, the bottom surface of said trench being at or below the lower 2DxG channel; and

a gate electrode located over said upper 2DxG channel, said gate electrode located within said trench, said gate electrode having a top and a bottom surface, the bottom surface of said gate electrode being in juxtaposition with the first sidewall surface, the bottom surface and the second sidewall surface of said trench:

wherein all of said 2DxG channels are either 2DEG channels or 2DHG channels, thereby creating a unipolar device.