Inhibiting background plating
Methods include selectively depositing a phase change resist having high light transmittance onto a dielectric to form a pattern, etching away portions of the dielectric not covered by the resist and depositing a metal seed layer on the etched portions of the dielectric. A metal layer is then deposited on the metal seed layer by light induced plating.
1. A method comprising:
a) providing a doped semiconductor comprising an n doped front side and a p doped back side, and a dielectric layer covering the n doped front side of the doped semiconductor;
b) selectively depositing a phase change resist having a light transmission of 30% or greater onto the dielectric layer to form a pattern on the dielectric layer;
c) etching away sections of the dielectric layer not covered with the phase change resist to expose sections of the n doped front side of the doped semiconductor;
d) depositing a metal seed layer on the exposed sections of the n doped front side of the doped semiconductor; and
e) depositing a metal layer on the metal seed layer by light induced plating.
2. The method of claim 1 , wherein the phase change resist comprises one or more waxes.
3. The method of claim 1 , wherein the phase change resist comprises one or more polyamide resins.
4. The method of claim 1 , wherein etching is done with an acid or a buffered oxide.
5. The method of claim 1 , wherein the phase change resist is selectively deposited by ink jetting, aerosol spray, screen printing or lithography.
6. The method of claim 1 , wherein the metal seed layer is nickel, palladium or silver.
7. The method of claim 1 , wherein the metal layer is copper or silver.
8. The method of claim 1 , further comprising a step of curing the phase change resist.
9. The method of claim 1 , further comprising a step of stripping the phase change resist.
10. The method of claim 1 , wherein the phase change resist is deposited as a liquid, semi-solid or gel.