Implementing a jump instruction in a dynamic translator that uses instruction code translation and just-in-time compilation
Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process. A system implementing the aforementioned translator may improve performance and speed associated with executing non-native instructions by optimizing the use of instruction codes and JIT-compiled native instructions corresponding to the instruction codes when executing the non-native instructions.
1. A method for implementing a jump instruction, comprising:
interpreting, by a processor, a first non-native instruction to generate a first instruction code after an initial scheduling of the first non-native instruction for execution;
storing, by the processor, the first instruction code and an address of a target instruction code pointed to by the first instruction code, wherein the address corresponds to an address in a shadow memory;
determining, by the processor, if a second instruction code is available at the shadow memory address of the target instruction code pointed to by the first instruction code;
compiling, by the processor, during a subsequent scheduling of the first non-native instruction for execution, and without reinterpreting the first non-native instruction during the subsequent scheduling, at least the first instruction code and the second instruction code, both retrieved from the shadow memory, as a group to generate a native instruction path when it is determined that the second instruction code is available in the shadow memory; and
defining a maximum number of target instruction codes for the first instruction code; and
compiling no more than the maximum number of target instruction codes with the first instruction code to generate the native instruction path.
2. The method of claim 1 , wherein the native instruction path comprises at least a first native instruction corresponding to the first instruction code and a second native instruction corresponding to the second instruction code.
3. The method of claim 1 , further comprising:
interpreting a non-native instruction corresponding to the second instruction code to generate the second instruction code when is determined that the second instruction code is not available at the shadow memory address of the target instruction code; and
compiling at least the first instruction code and the second instruction code as a group to generate the native instruction path when it is determined that the second instruction code is not available at the shadow memory address of the target instruction code.
4. The method of claim 3 , wherein the native instruction path comprises at least a first native instruction corresponding to the first instruction code and a second native instruction corresponding to the second instruction code.
5. The method of claim 1 , wherein the target instruction code is the target instruction code for a plurality of instruction codes and the first instruction code points to a plurality of target instruction codes.
6. A computer program product for implementing a jump instruction, comprising:
a non-transitory computer-readable medium comprising:
code to interpret a first non-native instruction to generate a first instruction code after an initial scheduling of the first non-native instruction for execution;
code to store the first instruction code and an address of a target instruction code pointed to by the first instruction code, wherein the address corresponds to an address in a shadow memory;
code to determine if a second instruction code is available at the shadow memory address of the target instruction code pointed to by the first instruction code; and
code to compile, during a subsequent scheduling of the first non-native instruction for execution, and without reinterpreting the first non-native instruction during the subsequent scheduling, at least the first instruction code and the second instruction code, both retrieved from the shadow memory, as a group to generate a native instruction path when it is determined that the second instruction code is available in the shadow memory and
code to define a maximum number of target instruction codes for the first instruction code; and
code to compile no more than the maximum number of target instruction codes with the first instruction code to generate the native instruction path.
7. The computer program product of claim 6 , wherein the native instruction path comprises at least a first native instruction corresponding to the first instruction code and a second native instruction corresponding to the second instruction code.
8. The computer program product of claim 6 , in which the medium further comprises:
code to interpret a non-native instruction corresponding to the second instruction code to generate the second instruction code when is determined that the second instruction code is not available at the shadow memory address of the target instruction code; and
code to compile at least the first instruction code and the second instruction code as a group to generate the native instruction path when it is determined that the second instruction code is not available at the shadow memory address of the target instruction code.
9. The computer program product of claim 8 , wherein the native instruction path comprises at least a first native instruction corresponding to the first instruction code and a second native instruction corresponding to the second instruction code.
10. The computer program product of claim 6 , wherein the target instruction code is the target instruction code for a plurality of instruction codes and the first instruction code points to a plurality of target instruction codes.
11. An apparatus for implementing a jump instruction, comprising:
a processor; and
a memory coupled to the processor, in which the processor is configured:
to interpret a first non-native instruction to generate a first instruction code after an initial scheduling of the first non-native instruction for execution;
to store the first instruction code and an address of a target instruction code pointed to by the first instruction code, wherein the address corresponds to an address in a shadow memory;
to determine if a second instruction code is available at the shadow memory address of the target instruction code pointed to by the first instruction code; and
to compile, during a subsequent scheduling of the first non-native instruction for execution, and without reinterpreting the first non-native instruction during the subsequent scheduling, at least the first instruction code and the second instruction code, both retrieved from the shadow memory, as a group to generate a native instruction path when it is determined that the second instruction code is available in the shadow; and
to define a maximum number of target instruction codes for the first instruction code; and
to compile no more than the maximum number of target instruction codes with the first instruction code to generate the native instruction path.
12. The apparatus of claim 11 , wherein the native instruction path comprises at least a first native instruction corresponding to the first instruction code and a second native instruction corresponding to the second instruction code.
13. The apparatus of claim 11 , in which the processor is further configured:
to interpret a non-native instruction corresponding to the second instruction code to generate the second instruction code when it is determined that the second instruction code is not available at the shadow memory address of the target instruction code; and
to compile at least the first instruction code and the second instruction code as a group to generate the native instruction path when it is determined that the second instruction code is not available at the shadow memory address of the target instruction code.
14. The apparatus of claim 13 , wherein the native instruction path comprises at least a first native instruction corresponding to the first instruction code and a second native instruction corresponding to the second instruction code.
15. The apparatus of claim 11 , wherein the target instruction code is the target instruction code for a plurality of instruction codes and the first instruction code points to a plurality of target instruction codes.